上传PL工程
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@@ -0,0 +1,479 @@
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{
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||||
"graphjs": {
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||||
"version": "1.0",
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||||
"keys": [
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{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
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"type": "string",
|
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"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
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"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
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||||
"type": "string",
|
||||
"for": "node"
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||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
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||||
"type": "string",
|
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"for": "node"
|
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},
|
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{
|
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"abrv": "MX",
|
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"name": "master_instance",
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"type": "string",
|
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"for": "node"
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},
|
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{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
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||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
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||||
"type": "string",
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"for": "node"
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||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
|
||||
"abrv": "SI",
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||||
"name": "slave_interface",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MM",
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||||
"name": "slave_memmap",
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||||
"type": "string",
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"for": "node"
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||||
},
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||||
{
|
||||
"abrv": "SS",
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||||
"name": "slave_segment",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
|
||||
"abrv": "SV",
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||||
"name": "slave_vlnv",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "TM",
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||||
"name": "memory_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
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||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
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||||
"type": "int",
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||||
"for": "edge"
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||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
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||||
"desc": "Assignment Coordinate"
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||||
},
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||||
{
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||||
"abrv": "ACE",
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||||
"desc": "Excluded Assign Coordinate"
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||||
},
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||||
{
|
||||
"abrv": "APX",
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||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
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||||
}
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||||
],
|
||||
"vertices": {
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||||
"V0": {
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||||
"VM": "design_a9_1",
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||||
"VT": "BC"
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||||
},
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||||
"V1": {
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||||
"VH": "2",
|
||||
"VM": "design_a9_1",
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||||
"VT": "VR"
|
||||
},
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||||
"V2": {
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||||
"VH": "2",
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||||
"VT": "PM",
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||||
"TU": "active"
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||||
},
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||||
"V3": {
|
||||
"VT": "AC",
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||||
"BA": "0x00000000",
|
||||
"HA": "0x1FFFFFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data_MM2S",
|
||||
"MX": "/axi_dma_0",
|
||||
"MI": "M_AXI_MM2S",
|
||||
"MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
|
||||
"MV": "xilinx.com:ip:axi_dma:7.1",
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||||
"SX": "/processing_system7_0",
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||||
"SI": "S_AXI_HP0",
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||||
"SS": "HP0_DDR_LOWOCM",
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||||
"SV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"TM": "both",
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||||
"TU": "memory"
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||||
},
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||||
"V4": {
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||||
"VT": "AC",
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||||
"BA": "0x00000000",
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||||
"HA": "0x1FFFFFFF",
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||||
"BP": "C_BASEADDR",
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||||
"HP": "C_HIGHADDR",
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||||
"MA": "Data_S2MM",
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||||
"MX": "/axi_dma_1",
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||||
"MI": "M_AXI_S2MM",
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||||
"MS": "SEG_processing_system7_0_HP0_DDR_LOWOCM",
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||||
"MV": "xilinx.com:ip:axi_dma:7.1",
|
||||
"SX": "/processing_system7_0",
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||||
"SI": "S_AXI_HP0",
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||||
"SS": "HP0_DDR_LOWOCM",
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||||
"SV": "xilinx.com:ip:processing_system7:5.5",
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||||
"TM": "both",
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||||
"TU": "memory"
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||||
},
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||||
"V5": {
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||||
"VT": "AC",
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||||
"BA": "0x40000000",
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||||
"HA": "0x40001FFF",
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||||
"BP": "C_S_AXI_BASEADDR",
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||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
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||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
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||||
"MS": "SEG_axi_bram_ctrl_0_Mem0",
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||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_0",
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||||
"SI": "S_AXI",
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||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
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||||
"TU": "memory"
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||||
},
|
||||
"V6": {
|
||||
"VT": "AC",
|
||||
"BA": "0x40400000",
|
||||
"HA": "0x4040FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_dma_0_Reg",
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||||
"MV": "xilinx.com:ip:processing_system7:5.5",
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||||
"SX": "/axi_dma_0",
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||||
"SI": "S_AXI_LITE",
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||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_dma:7.1",
|
||||
"TM": "both",
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||||
"TU": "register"
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||||
},
|
||||
"V7": {
|
||||
"VT": "AC",
|
||||
"BA": "0x40410000",
|
||||
"HA": "0x4041FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_dma_1_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_dma_1",
|
||||
"SI": "S_AXI_LITE",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_dma:7.1",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V8": {
|
||||
"VT": "AC",
|
||||
"BA": "0x41200000",
|
||||
"HA": "0x4120FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
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||||
"MS": "SEG_axi_gpio_0_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_gpio_0",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V9": {
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||||
"VT": "AC",
|
||||
"BA": "0x41600000",
|
||||
"HA": "0x4160FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_iic_0_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_iic_0",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_iic:2.1",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V10": {
|
||||
"VT": "AC",
|
||||
"BA": "0x41610000",
|
||||
"HA": "0x4161FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_iic_1_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_iic_1",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_iic:2.1",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V11": {
|
||||
"VT": "AC",
|
||||
"BA": "0x42000000",
|
||||
"HA": "0x42001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_1_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_1",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
},
|
||||
"V12": {
|
||||
"VT": "AC",
|
||||
"BA": "0x44000000",
|
||||
"HA": "0x44001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_2_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_2",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
},
|
||||
"V13": {
|
||||
"VT": "AC",
|
||||
"BA": "0x46000000",
|
||||
"HA": "0x46001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_3_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_3",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
},
|
||||
"V14": {
|
||||
"VT": "AC",
|
||||
"BA": "0x48000000",
|
||||
"HA": "0x48001FFF",
|
||||
"BP": "C_S_AXI_BASEADDR",
|
||||
"HP": "C_S_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_bram_ctrl_4_Mem0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_bram_ctrl_4",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Mem0",
|
||||
"SV": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"TM": "both",
|
||||
"TU": "memory"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V5",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V6",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V7",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V8",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V9",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V10",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V11",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V12",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V13",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V14",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_bram_ctrl_0_0",
|
||||
"cell_name": "axi_bram_ctrl_0",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_bram_ctrl_1_0",
|
||||
"cell_name": "axi_bram_ctrl_1",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_bram_ctrl_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_bram_ctrl_2_0",
|
||||
"cell_name": "axi_bram_ctrl_2",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_bram_ctrl_2_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_bram_ctrl_3_0",
|
||||
"cell_name": "axi_bram_ctrl_3",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_bram_ctrl_3_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_bram_ctrl_4_0",
|
||||
"cell_name": "axi_bram_ctrl_4",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_bram_ctrl_4_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+969
@@ -0,0 +1,969 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_dma_0_0",
|
||||
"cell_name": "axi_dma_0",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_dma_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_mm2s_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_mm2s_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rready": [ { "direction": "out" } ],
|
||||
"mm2s_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axis_mm2s_tkeep": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axis_mm2s_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axis_mm2s_tlast": [ { "direction": "out" } ],
|
||||
"mm2s_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_MM2S",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "128", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "m_axi_mm2s_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "m_axi_mm2s_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "m_axi_mm2s_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "m_axi_mm2s_arlen" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_mm2s_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_mm2s_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "m_axi_mm2s_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_mm2s_arvalid" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_mm2s_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "m_axi_mm2s_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_mm2s_rready" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_mm2s_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_mm2s_rvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_MM2S": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_mm2s_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_mm2s_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_mm2s_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_mm2s_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_mm2s_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "mm2s_introut" } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_mm2s_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mm2s_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_MM2S": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+974
@@ -0,0 +1,974 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_dma_1_0",
|
||||
"cell_name": "axi_dma_1",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_dma_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "8", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in" } ],
|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "128", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+387
@@ -0,0 +1,387 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_gpio_0_0",
|
||||
"cell_name": "axi_gpio_0",
|
||||
"component_reference": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "30",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "30" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ip2intc_irpt": [ { "direction": "out" } ],
|
||||
"gpio_io_i": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"gpio2_io_o": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"IP2INTC_IRQ": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"GPIO": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_I": [ { "physical_name": "gpio_io_i" } ]
|
||||
}
|
||||
},
|
||||
"GPIO2": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO2_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_O": [ { "physical_name": "gpio2_io_o" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GPIO_DATA": {
|
||||
"address_offset": "0x0",
|
||||
"size": 8,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "Channel-1 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_1_GPIO_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO_TRI": {
|
||||
"address_offset": "0x4",
|
||||
"size": 8,
|
||||
"display_name": "Channel_1_GPIO_TRI",
|
||||
"description": "Channel-1 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_1_GPIO_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_DATA": {
|
||||
"address_offset": "0x8",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "Channel-2 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_2_GPIO_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_TRI": {
|
||||
"address_offset": "0xC",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_TRI",
|
||||
"description": "Channel-2 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_2_GPIO_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GIER": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "Global_Interrupt_Enable register",
|
||||
"description": "Global_Interrupt_Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Global_Interrupt_Enable": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "Global_Interrupt_Enable",
|
||||
"description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_IER": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Enable register",
|
||||
"description": "IP Interrupt Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_1_Interrupt_Enable": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Enable",
|
||||
"description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Channel_2_Interrupt_Enable": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Enable",
|
||||
"description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_ISR": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Status register",
|
||||
"description": "IP Interrupt Status register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_1_Interrupt_Status": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Status",
|
||||
"description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Channel_2_Interrupt_Status": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Status",
|
||||
"description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+863
@@ -0,0 +1,863 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_iic_0_0",
|
||||
"cell_name": "axi_iic_0",
|
||||
"component_reference": "xilinx.com:ip:axi_iic:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SDA_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_iic_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TEN_BIT_ADR": [ { "value": "7_bit", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ACLK_FREQ_MHZ": [ { "value": "100.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_GPO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "0x00", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_SCL_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IIC_FREQ_KHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"IIC_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_STATIC_TIMING_REG_WIDTH": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_TIMING_REG_WIDTH": [ { "value": "32", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_DISABLE_SETUP_VIOLATION_CHECK": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_IIC_FREQ": [ { "value": "100000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TEN_BIT_ADR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCL_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SMBUS_PMBUS_HOST": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_SETUP_VIOLATION_CHECK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_STATIC_TIMING_REG_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIMING_REG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"iic2intc_irpt": [ { "direction": "out" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in" } ],
|
||||
"sda_i": [ { "direction": "in" } ],
|
||||
"sda_o": [ { "direction": "out" } ],
|
||||
"sda_t": [ { "direction": "out" } ],
|
||||
"scl_i": [ { "direction": "in" } ],
|
||||
"scl_o": [ { "direction": "out" } ],
|
||||
"scl_t": [ { "direction": "out" } ],
|
||||
"gpo": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"INTERRUPT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "iic2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"IIC": {
|
||||
"vlnv": "xilinx.com:interface:iic:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "IIC_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"SCL_I": [ { "physical_name": "scl_i" } ],
|
||||
"SCL_O": [ { "physical_name": "scl_o" } ],
|
||||
"SCL_T": [ { "physical_name": "scl_t" } ],
|
||||
"SDA_I": [ { "physical_name": "sda_i" } ],
|
||||
"SDA_O": [ { "physical_name": "sda_o" } ],
|
||||
"SDA_T": [ { "physical_name": "sda_t" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GIE": {
|
||||
"address_offset": "0x1c",
|
||||
"size": 32,
|
||||
"display_name": "GIE",
|
||||
"description": "Global Interrupt Enable Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"GIE": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "GIE",
|
||||
"description": "Global Interrupt Enable\n0 - All Interrupts disabled; no interrupt (even if unmasked in IER) possible from AXI IIC core\n1 - Unmasked AXI IIC core interrupts are passed to processor\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ISR": {
|
||||
"address_offset": "0x020",
|
||||
"size": 32,
|
||||
"display_name": "ISR",
|
||||
"description": "Interrupt Status Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0xd0",
|
||||
"fields": {
|
||||
"int0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "int0",
|
||||
"description": "Interrupt0 - Arbitration Lost\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int1": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "int1",
|
||||
"description": "Interrupt1 - Transmit Error/Slave Transmit Complete\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int2": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "int2",
|
||||
"description": "Interrupt2 - Transmit FIFO Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int3": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "int3",
|
||||
"description": "Interrupt3 - Recieve FIFO FULL\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int4": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "int4",
|
||||
"description": "Interrupt4 - IIC Bus is Not Busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int5": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "int5",
|
||||
"description": "Interrupt5 - Addressed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int6": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "int6",
|
||||
"description": "Interrupt6 - Not Addessed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int7": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "int7",
|
||||
"description": "Interrupt7 - Transmit FIFO Half Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IER": {
|
||||
"address_offset": "0x028",
|
||||
"size": 32,
|
||||
"display_name": "IER",
|
||||
"description": "Interrupt Enable Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"int0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "int0",
|
||||
"description": "Interrupt0 - Arbitration Lost\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int1": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "int1",
|
||||
"description": "Interrupt1 - Transmit Error/Slave Transmit Complete\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int2": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "int2",
|
||||
"description": "Interrupt2 - Transmit FIFO Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int3": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "int3",
|
||||
"description": "Interrupt3 - Recieve FIFO FULL\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int4": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "int4",
|
||||
"description": "Interrupt4 - IIC Bus is Not Busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int5": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "int5",
|
||||
"description": "Interrupt5 - Addressed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int6": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "int6",
|
||||
"description": "Interrupt6 - Not Addessed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int7": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "int7",
|
||||
"description": "Interrupt7 - Transmit FIFO Half Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SOFTR": {
|
||||
"address_offset": "0x040",
|
||||
"size": 32,
|
||||
"display_name": "SOFTR",
|
||||
"description": "Soft Reset Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"RKEY": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "RKEY",
|
||||
"description": "Reset Key - Firmware must write a value of 0xA to this field to\n cause a soft reset of the Interrupt registers of AXI IIC controller.\n Writing any other value results in an AXI transaction\n acknowledgement with SLVERR and no reset occurs.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"CR": {
|
||||
"address_offset": "0x100",
|
||||
"size": 32,
|
||||
"display_name": "CR",
|
||||
"description": "Control Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"EN": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "AXI IIC Enable",
|
||||
"description": "This bit must be set before any other CR bits have any effect\n0 - resets and disables the AXI IIC controller but not the registers or FIFOs\n1 - enables the AXI IIC controller\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TX_FIFO_Reset": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Reset",
|
||||
"description": "This bit must be set to flush the FIFO if either (a) arbitration is lost or (b) if a transmit error occurs\n0 - transmit FIFO normal operation\n1 - resets the transmit FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"MSMS": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Master/Slave Mode Select",
|
||||
"description": "When this bit is changed from 0 to 1, the\nAXI IIC bus interface generates a START condition in master mode. When\nthis bit is cleared, a STOP condition is generated and the AXI IIC bus\ninterface switches to slave mode. When this bit is cleared by the\nhardware, because arbitration for the bus has been lost, a STOP\ncondition is not generated\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TX": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit/Recieve Mode Select",
|
||||
"description": "This bit selects the direction of master/slave transfers.\n0 - selects an AXI IIC receive\n1 - selects an AXI IIC transmit\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TXAK": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit Acknowledgement",
|
||||
"description": "This bit specifies the value driven onto\nthe sda line during acknowledge cycles for both master and slave recievers.\n0 - acknowledge\n1 - not-acknowledge\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"RSTA": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "Repeated Start",
|
||||
"description": "Writing a 1 to this bit generates a repeated START \ncondition on the bus if the AXI IIC bus interface is the current bus\nmaster. Attempting a repeated START at the wrong time, if the bus is\nowned by another master, results in a loss of arbitration. This bit is reset\nwhen the repeated start occurs. This bit must be set prior to writing the\nnew address to the TX_FIFO or DTR\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"GC_EN": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "General Call Enable",
|
||||
"description": "Setting this bit High allows the AXI IIC to respond to a general call address.\n0 - General Call Disabled\n1 - General Call Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SR": {
|
||||
"address_offset": "0x104",
|
||||
"size": 32,
|
||||
"display_name": "SR",
|
||||
"description": "Status Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"ABGC": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Addressed By a General Call",
|
||||
"description": "This bit is set to 1 when another master has issued a general call and\nthe general call enable bit is set to 1, CR(6) = 1.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"AAS": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Addressed As Slave",
|
||||
"description": "When the address on the IIC bus matches the slave address in the Address register (ADR), the IIC bus interface\nis being addressed as a slave and switches to slave mode. If 10-bit addressing is selected this device only responds to a 10-bit\naddress or general call if enabled. This bit is cleared when a stop\ncondition is detected or a repeated start occurs.\n0 - indicates not being addressed as a slave\n1 - indicates being addressed as a slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"BB": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Bus Busy",
|
||||
"description": "This bit indicates the status of the IIC bus. This bit is set\nwhen a START condition is detected and cleared when a STOP\ncondition is detected.\n0 - indicates the bus is idle\n1 - indicates the bus is busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"ARW": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Slave Read/Write",
|
||||
"description": "When the IIC bus interface has been addressed as a slave (AAS is set), \nthis bit indicates the value of the read/write bit sent by the master.\nThis bit is only valid when a complete transfer has occurred and\nno other transfers have been initiated.\n0 - indicates master writing to slave\n1 - indicates master reading from slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"TX_FIFO_Full": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Full",
|
||||
"description": "This bit is set High when the transmit FIFO is full.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"RX_FIFO_Full": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "Recieve FUFO Full",
|
||||
"description": "This bit is set High when the receive FIFO is full.\nThis bit is set only when all 16 locations in the FIFO are full,\nregardless of the compare value field of the RX_FIFO_PIRQ register.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"RX_FIFO_Empty": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "Receive FIFO empty",
|
||||
"description": "This is set High when the receive FIFO is empty.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"TX_FIFO_Empty": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Empty",
|
||||
"description": "This is set High when the transmit FIFO is empty.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TX_FIFO": {
|
||||
"address_offset": "0x108",
|
||||
"size": 32,
|
||||
"display_name": "TX_FIFO",
|
||||
"description": "Transmit FIFO Register",
|
||||
"access": "write-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"D7_D0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "AXI IIC Transmit Data",
|
||||
"description": "If the dynamic stop bit is used and the AXI IIC is a master receiver,\nthe value is the number of bytes to receive.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
},
|
||||
"Start": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Start",
|
||||
"description": "The dynamic start bit can be used to send a start or repeated start sequence on the\nIIC bus. A start sequence is generated if the MSMS = 0, a\nrepeated start sequence is generated if the MSMS = 1.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
},
|
||||
"Stop": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Stop",
|
||||
"description": "The dynamic stop bit can be used to send an IIC stop\nsequence on the IIC bus after the last byte has been transmitted or received.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO": {
|
||||
"address_offset": "0x10C",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO",
|
||||
"description": "Recieve FIFO Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"D7_D0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "IIC Receive Data",
|
||||
"description": "IIC Receive Data\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ADR": {
|
||||
"address_offset": "0x110",
|
||||
"size": 32,
|
||||
"display_name": "ADR",
|
||||
"description": "Slave Address Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Slave_Address": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 7,
|
||||
"display_name": "Slave Address",
|
||||
"description": "Address used by the IIC bus interface when in slave mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TX_FIFO_OCY": {
|
||||
"address_offset": "0x114",
|
||||
"size": 32,
|
||||
"display_name": "TX_FIFO_OCY",
|
||||
"description": "Transmit FIFO Occupency Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Occupancy_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Occupancy_Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 indicates that\n10 locations are full in the FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO_OCY": {
|
||||
"address_offset": "0x118",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO_OCY",
|
||||
"description": "Recieve FIFO Occupency Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Occupancy_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Occupancy_Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 indicates that\n10 locations are full in the FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TEN_ADR": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "TEN_ADR",
|
||||
"description": "Slave Ten Bit Address Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"MSB_of_Slave_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 3,
|
||||
"display_name": "MSB_of_Slave_Address",
|
||||
"description": "Three MSBs of the 10-bit address used by the AXI IIC bus interface when in slave mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO_PIRQ": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO_PIRQ",
|
||||
"description": "Recieve FIFO Programmable Depth Interrupt Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Compare_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Compare Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 implies that when\n10 locations in the receive FIFO are filled, the receive FIFO\ninterrupt is set.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPO": {
|
||||
"address_offset": "0x124",
|
||||
"size": 32,
|
||||
"display_name": "GPO",
|
||||
"description": "General Purpose Output Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"General_Purpose_Outputs": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "General Purpose Outputs",
|
||||
"description": "The LSB (Bit[0]) is the first bit populated\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUSTA": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "TSUSTA",
|
||||
"description": "Timing Parameter TSUSTA Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUSTA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUSTA",
|
||||
"description": "Setup time for a repeated START condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUSTO": {
|
||||
"address_offset": "0x12C",
|
||||
"size": 32,
|
||||
"display_name": "TSUSTO",
|
||||
"description": "Timing Parameter TSUSTO Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUSTO": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUSTO",
|
||||
"description": "Setup time for a repeated STOP condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THDSTA": {
|
||||
"address_offset": "0x130",
|
||||
"size": 32,
|
||||
"display_name": "THDSTA",
|
||||
"description": "Timing Parameter THDSTA Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THDSTA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THDSTA",
|
||||
"description": "Hold time for a repeated START condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUDAT": {
|
||||
"address_offset": "0x134",
|
||||
"size": 32,
|
||||
"display_name": "TSUDAT",
|
||||
"description": "Timing Parameter TSUDAT Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUDAT": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUDAT",
|
||||
"description": "Data Setup time\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TBUF": {
|
||||
"address_offset": "0x138",
|
||||
"size": 32,
|
||||
"display_name": "TBUF",
|
||||
"description": "Timing Parameter TBUF Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TBUF": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TBUF",
|
||||
"description": "Bus free time between a STOP and START condition\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THIGH": {
|
||||
"address_offset": "0x13C",
|
||||
"size": 32,
|
||||
"display_name": "THIGH",
|
||||
"description": "Timing Parameter THIGH Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THIGH": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THIGH",
|
||||
"description": "High Period of the scl clock.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TLOW": {
|
||||
"address_offset": "0x140",
|
||||
"size": 32,
|
||||
"display_name": "TLOW",
|
||||
"description": "Timing Parameter TLOW Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TLOW": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TLOW",
|
||||
"description": "Low Period of scl clock.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THDDAT": {
|
||||
"address_offset": "0x144",
|
||||
"size": 32,
|
||||
"display_name": "THDDAT",
|
||||
"description": "Timing Parameter THDDAT Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THDDAT": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THDDAT",
|
||||
"description": "Data Hold time\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+863
@@ -0,0 +1,863 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_iic_1_0",
|
||||
"cell_name": "axi_iic_1",
|
||||
"component_reference": "xilinx.com:ip:axi_iic:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SDA_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_iic_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TEN_BIT_ADR": [ { "value": "7_bit", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ACLK_FREQ_MHZ": [ { "value": "100.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_GPO_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "0x00", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_SCL_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IIC_FREQ_KHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"IIC_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_STATIC_TIMING_REG_WIDTH": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_TIMING_REG_WIDTH": [ { "value": "32", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_DISABLE_SETUP_VIOLATION_CHECK": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_IIC_FREQ": [ { "value": "100000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TEN_BIT_ADR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCL_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_INERTIAL_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SDA_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SMBUS_PMBUS_HOST": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_SETUP_VIOLATION_CHECK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_STATIC_TIMING_REG_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIMING_REG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"iic2intc_irpt": [ { "direction": "out" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in" } ],
|
||||
"sda_i": [ { "direction": "in" } ],
|
||||
"sda_o": [ { "direction": "out" } ],
|
||||
"sda_t": [ { "direction": "out" } ],
|
||||
"scl_i": [ { "direction": "in" } ],
|
||||
"scl_o": [ { "direction": "out" } ],
|
||||
"scl_t": [ { "direction": "out" } ],
|
||||
"gpo": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"INTERRUPT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "iic2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"IIC": {
|
||||
"vlnv": "xilinx.com:interface:iic:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "IIC_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"SCL_I": [ { "physical_name": "scl_i" } ],
|
||||
"SCL_O": [ { "physical_name": "scl_o" } ],
|
||||
"SCL_T": [ { "physical_name": "scl_t" } ],
|
||||
"SDA_I": [ { "physical_name": "sda_i" } ],
|
||||
"SDA_O": [ { "physical_name": "sda_o" } ],
|
||||
"SDA_T": [ { "physical_name": "sda_t" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GIE": {
|
||||
"address_offset": "0x1c",
|
||||
"size": 32,
|
||||
"display_name": "GIE",
|
||||
"description": "Global Interrupt Enable Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"GIE": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "GIE",
|
||||
"description": "Global Interrupt Enable\n0 - All Interrupts disabled; no interrupt (even if unmasked in IER) possible from AXI IIC core\n1 - Unmasked AXI IIC core interrupts are passed to processor\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ISR": {
|
||||
"address_offset": "0x020",
|
||||
"size": 32,
|
||||
"display_name": "ISR",
|
||||
"description": "Interrupt Status Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0xd0",
|
||||
"fields": {
|
||||
"int0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "int0",
|
||||
"description": "Interrupt0 - Arbitration Lost\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int1": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "int1",
|
||||
"description": "Interrupt1 - Transmit Error/Slave Transmit Complete\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int2": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "int2",
|
||||
"description": "Interrupt2 - Transmit FIFO Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int3": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "int3",
|
||||
"description": "Interrupt3 - Recieve FIFO FULL\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int4": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "int4",
|
||||
"description": "Interrupt4 - IIC Bus is Not Busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int5": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "int5",
|
||||
"description": "Interrupt5 - Addressed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int6": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "int6",
|
||||
"description": "Interrupt6 - Not Addessed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int7": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "int7",
|
||||
"description": "Interrupt7 - Transmit FIFO Half Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IER": {
|
||||
"address_offset": "0x028",
|
||||
"size": 32,
|
||||
"display_name": "IER",
|
||||
"description": "Interrupt Enable Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"int0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "int0",
|
||||
"description": "Interrupt0 - Arbitration Lost\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int1": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "int1",
|
||||
"description": "Interrupt1 - Transmit Error/Slave Transmit Complete\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int2": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "int2",
|
||||
"description": "Interrupt2 - Transmit FIFO Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int3": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "int3",
|
||||
"description": "Interrupt3 - Recieve FIFO FULL\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int4": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "int4",
|
||||
"description": "Interrupt4 - IIC Bus is Not Busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int5": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "int5",
|
||||
"description": "Interrupt5 - Addressed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int6": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "int6",
|
||||
"description": "Interrupt6 - Not Addessed As Slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"int7": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "int7",
|
||||
"description": "Interrupt7 - Transmit FIFO Half Empty\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SOFTR": {
|
||||
"address_offset": "0x040",
|
||||
"size": 32,
|
||||
"display_name": "SOFTR",
|
||||
"description": "Soft Reset Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"RKEY": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "RKEY",
|
||||
"description": "Reset Key - Firmware must write a value of 0xA to this field to\n cause a soft reset of the Interrupt registers of AXI IIC controller.\n Writing any other value results in an AXI transaction\n acknowledgement with SLVERR and no reset occurs.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"CR": {
|
||||
"address_offset": "0x100",
|
||||
"size": 32,
|
||||
"display_name": "CR",
|
||||
"description": "Control Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"EN": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "AXI IIC Enable",
|
||||
"description": "This bit must be set before any other CR bits have any effect\n0 - resets and disables the AXI IIC controller but not the registers or FIFOs\n1 - enables the AXI IIC controller\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TX_FIFO_Reset": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Reset",
|
||||
"description": "This bit must be set to flush the FIFO if either (a) arbitration is lost or (b) if a transmit error occurs\n0 - transmit FIFO normal operation\n1 - resets the transmit FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"MSMS": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Master/Slave Mode Select",
|
||||
"description": "When this bit is changed from 0 to 1, the\nAXI IIC bus interface generates a START condition in master mode. When\nthis bit is cleared, a STOP condition is generated and the AXI IIC bus\ninterface switches to slave mode. When this bit is cleared by the\nhardware, because arbitration for the bus has been lost, a STOP\ncondition is not generated\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TX": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit/Recieve Mode Select",
|
||||
"description": "This bit selects the direction of master/slave transfers.\n0 - selects an AXI IIC receive\n1 - selects an AXI IIC transmit\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"TXAK": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit Acknowledgement",
|
||||
"description": "This bit specifies the value driven onto\nthe sda line during acknowledge cycles for both master and slave recievers.\n0 - acknowledge\n1 - not-acknowledge\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"RSTA": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "Repeated Start",
|
||||
"description": "Writing a 1 to this bit generates a repeated START \ncondition on the bus if the AXI IIC bus interface is the current bus\nmaster. Attempting a repeated START at the wrong time, if the bus is\nowned by another master, results in a loss of arbitration. This bit is reset\nwhen the repeated start occurs. This bit must be set prior to writing the\nnew address to the TX_FIFO or DTR\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"GC_EN": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "General Call Enable",
|
||||
"description": "Setting this bit High allows the AXI IIC to respond to a general call address.\n0 - General Call Disabled\n1 - General Call Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SR": {
|
||||
"address_offset": "0x104",
|
||||
"size": 32,
|
||||
"display_name": "SR",
|
||||
"description": "Status Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"ABGC": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Addressed By a General Call",
|
||||
"description": "This bit is set to 1 when another master has issued a general call and\nthe general call enable bit is set to 1, CR(6) = 1.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"AAS": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Addressed As Slave",
|
||||
"description": "When the address on the IIC bus matches the slave address in the Address register (ADR), the IIC bus interface\nis being addressed as a slave and switches to slave mode. If 10-bit addressing is selected this device only responds to a 10-bit\naddress or general call if enabled. This bit is cleared when a stop\ncondition is detected or a repeated start occurs.\n0 - indicates not being addressed as a slave\n1 - indicates being addressed as a slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"BB": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Bus Busy",
|
||||
"description": "This bit indicates the status of the IIC bus. This bit is set\nwhen a START condition is detected and cleared when a STOP\ncondition is detected.\n0 - indicates the bus is idle\n1 - indicates the bus is busy\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"ARW": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Slave Read/Write",
|
||||
"description": "When the IIC bus interface has been addressed as a slave (AAS is set), \nthis bit indicates the value of the read/write bit sent by the master.\nThis bit is only valid when a complete transfer has occurred and\nno other transfers have been initiated.\n0 - indicates master writing to slave\n1 - indicates master reading from slave\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"TX_FIFO_Full": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Full",
|
||||
"description": "This bit is set High when the transmit FIFO is full.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"RX_FIFO_Full": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "Recieve FUFO Full",
|
||||
"description": "This bit is set High when the receive FIFO is full.\nThis bit is set only when all 16 locations in the FIFO are full,\nregardless of the compare value field of the RX_FIFO_PIRQ register.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"RX_FIFO_Empty": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "Receive FIFO empty",
|
||||
"description": "This is set High when the receive FIFO is empty.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"TX_FIFO_Empty": {
|
||||
"bit_offset": 7,
|
||||
"bit_width": 1,
|
||||
"display_name": "Transmit FIFO Empty",
|
||||
"description": "This is set High when the transmit FIFO is empty.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TX_FIFO": {
|
||||
"address_offset": "0x108",
|
||||
"size": 32,
|
||||
"display_name": "TX_FIFO",
|
||||
"description": "Transmit FIFO Register",
|
||||
"access": "write-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"D7_D0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "AXI IIC Transmit Data",
|
||||
"description": "If the dynamic stop bit is used and the AXI IIC is a master receiver,\nthe value is the number of bytes to receive.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
},
|
||||
"Start": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Start",
|
||||
"description": "The dynamic start bit can be used to send a start or repeated start sequence on the\nIIC bus. A start sequence is generated if the MSMS = 0, a\nrepeated start sequence is generated if the MSMS = 1.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
},
|
||||
"Stop": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Stop",
|
||||
"description": "The dynamic stop bit can be used to send an IIC stop\nsequence on the IIC bus after the last byte has been transmitted or received.\n",
|
||||
"is_volatile": true,
|
||||
"access": "write-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO": {
|
||||
"address_offset": "0x10C",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO",
|
||||
"description": "Recieve FIFO Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"D7_D0": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 8,
|
||||
"display_name": "IIC Receive Data",
|
||||
"description": "IIC Receive Data\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ADR": {
|
||||
"address_offset": "0x110",
|
||||
"size": 32,
|
||||
"display_name": "ADR",
|
||||
"description": "Slave Address Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Slave_Address": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 7,
|
||||
"display_name": "Slave Address",
|
||||
"description": "Address used by the IIC bus interface when in slave mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TX_FIFO_OCY": {
|
||||
"address_offset": "0x114",
|
||||
"size": 32,
|
||||
"display_name": "TX_FIFO_OCY",
|
||||
"description": "Transmit FIFO Occupency Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Occupancy_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Occupancy_Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 indicates that\n10 locations are full in the FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO_OCY": {
|
||||
"address_offset": "0x118",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO_OCY",
|
||||
"description": "Recieve FIFO Occupency Register",
|
||||
"access": "read-only",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Occupancy_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Occupancy_Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 indicates that\n10 locations are full in the FIFO\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TEN_ADR": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "TEN_ADR",
|
||||
"description": "Slave Ten Bit Address Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"MSB_of_Slave_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 3,
|
||||
"display_name": "MSB_of_Slave_Address",
|
||||
"description": "Three MSBs of the 10-bit address used by the AXI IIC bus interface when in slave mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RX_FIFO_PIRQ": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "RX_FIFO_PIRQ",
|
||||
"description": "Recieve FIFO Programmable Depth Interrupt Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Compare_Value": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 4,
|
||||
"display_name": "Compare Value",
|
||||
"description": "Bit[3] is the MSB. A binary value of 1001 implies that when\n10 locations in the receive FIFO are filled, the receive FIFO\ninterrupt is set.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPO": {
|
||||
"address_offset": "0x124",
|
||||
"size": 32,
|
||||
"display_name": "GPO",
|
||||
"description": "General Purpose Output Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"General_Purpose_Outputs": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "General Purpose Outputs",
|
||||
"description": "The LSB (Bit[0]) is the first bit populated\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUSTA": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "TSUSTA",
|
||||
"description": "Timing Parameter TSUSTA Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUSTA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUSTA",
|
||||
"description": "Setup time for a repeated START condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUSTO": {
|
||||
"address_offset": "0x12C",
|
||||
"size": 32,
|
||||
"display_name": "TSUSTO",
|
||||
"description": "Timing Parameter TSUSTO Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUSTO": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUSTO",
|
||||
"description": "Setup time for a repeated STOP condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THDSTA": {
|
||||
"address_offset": "0x130",
|
||||
"size": 32,
|
||||
"display_name": "THDSTA",
|
||||
"description": "Timing Parameter THDSTA Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THDSTA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THDSTA",
|
||||
"description": "Hold time for a repeated START condition.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TSUDAT": {
|
||||
"address_offset": "0x134",
|
||||
"size": 32,
|
||||
"display_name": "TSUDAT",
|
||||
"description": "Timing Parameter TSUDAT Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TSUDAT": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TSUDAT",
|
||||
"description": "Data Setup time\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TBUF": {
|
||||
"address_offset": "0x138",
|
||||
"size": 32,
|
||||
"display_name": "TBUF",
|
||||
"description": "Timing Parameter TBUF Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TBUF": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TBUF",
|
||||
"description": "Bus free time between a STOP and START condition\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THIGH": {
|
||||
"address_offset": "0x13C",
|
||||
"size": 32,
|
||||
"display_name": "THIGH",
|
||||
"description": "Timing Parameter THIGH Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THIGH": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THIGH",
|
||||
"description": "High Period of the scl clock.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"TLOW": {
|
||||
"address_offset": "0x140",
|
||||
"size": 32,
|
||||
"display_name": "TLOW",
|
||||
"description": "Timing Parameter TLOW Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"TLOW": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "TLOW",
|
||||
"description": "Low Period of scl clock.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"THDDAT": {
|
||||
"address_offset": "0x144",
|
||||
"size": 32,
|
||||
"display_name": "THDDAT",
|
||||
"description": "Timing Parameter THDDAT Register",
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"THDDAT": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "THDDAT",
|
||||
"description": "Data Hold time\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+982
@@ -0,0 +1,982 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axi_smc_0",
|
||||
"cell_name": "axi_smc",
|
||||
"component_reference": "xilinx.com:ip:smartconnect:1.0",
|
||||
"ip_revision": "20",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_a9_1_axi_smc_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADVANCED_PROPERTIES": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"TLM_COMPONENT_NAME": [ { "value": "design_a9_1_axi_smc_0", "resolve_type": "generated", "usage": "simulation.tlm" } ],
|
||||
"HAS_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "20" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"S00_AXI_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S00_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S00_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_bid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S00_AXI_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S00_AXI_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_awaddr": [ { "direction": "out", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_wvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_araddr": [ { "direction": "out", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M01_AXI_awaddr": [ { "direction": "out", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M01_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M01_AXI_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"M01_AXI_wvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M01_AXI_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M01_AXI_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M01_AXI_bready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M01_AXI_araddr": [ { "direction": "out", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_arvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M01_AXI_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M01_AXI_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M01_AXI_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M01_AXI_rready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M02_AXI_awaddr": [ { "direction": "out", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
|
||||
"M02_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M02_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M02_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
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||||
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||||
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||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ]
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||||
},
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||||
"port_maps": {
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||||
"CLK": [ { "physical_name": "aclk" } ]
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||||
}
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||||
},
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||||
"RST.aresetn": {
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||||
"vlnv": "xilinx.com:signal:reset:1.0",
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||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
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||||
},
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||||
"port_maps": {
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||||
"RST": [ { "physical_name": "aresetn" } ]
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||||
}
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||||
},
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||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
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||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
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||||
"mode": "slave",
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"parameters": {
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
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||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
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|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "S00_AXI_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "S00_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S00_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S00_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S00_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S00_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S00_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S00_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S00_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S00_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S00_AXI_awready" } ],
|
||||
"WID": [ { "physical_name": "S00_AXI_wid" } ],
|
||||
"WDATA": [ { "physical_name": "S00_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S00_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S00_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S00_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S00_AXI_wready" } ],
|
||||
"BID": [ { "physical_name": "S00_AXI_bid" } ],
|
||||
"BRESP": [ { "physical_name": "S00_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S00_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S00_AXI_bready" } ],
|
||||
"ARID": [ { "physical_name": "S00_AXI_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "S00_AXI_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "S00_AXI_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "S00_AXI_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "S00_AXI_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "S00_AXI_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "S00_AXI_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "S00_AXI_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "S00_AXI_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "S00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "S00_AXI_arready" } ],
|
||||
"RID": [ { "physical_name": "S00_AXI_rid" } ],
|
||||
"RDATA": [ { "physical_name": "S00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "S00_AXI_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "S00_AXI_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "S00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "S00_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M00_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M00_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M00_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M00_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M00_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M00_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M00_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M00_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M00_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M00_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M00_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M00_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M00_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M00_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M00_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M00_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M01_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M01_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M01_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M01_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M01_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M01_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M01_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M01_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M01_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M01_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M01_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M01_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M01_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M01_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M01_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M01_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M01_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M01_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M01_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M01_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M02_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M02_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M02_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M02_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M02_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M02_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M02_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M02_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M02_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M02_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M02_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M02_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M02_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M02_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M02_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M02_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M02_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M02_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M02_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M02_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M03_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M03_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M03_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M03_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M03_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M03_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M03_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M03_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M03_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M03_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M03_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M03_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M03_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M03_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M03_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M03_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M03_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M03_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M03_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M03_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M04_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M04_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M04_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M04_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M04_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M04_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M04_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M04_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M04_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M04_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M04_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M04_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M04_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M04_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M04_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M04_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M04_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M04_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M04_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M04_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M05_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M05_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M05_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M05_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M05_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M05_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M05_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M05_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M05_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M05_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M05_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M05_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M05_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M05_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M05_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M05_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M05_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M05_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M05_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M05_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M06_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M06_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M06_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M06_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M06_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M06_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M06_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M06_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M06_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M06_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M06_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M06_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M06_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M06_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M06_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M06_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M06_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M06_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M06_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M06_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M07_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"AWREADY": [ { "physical_name": "M07_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M07_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M07_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M07_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M07_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M07_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M07_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M07_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M07_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M07_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M07_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M07_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M07_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M07_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M07_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M07_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M08_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "default_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M08_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M08_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M08_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M08_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M08_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M08_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M08_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M08_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M08_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M08_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M08_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M08_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M08_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M08_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M08_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M08_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M08_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M08_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M08_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"M09_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "13", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M09_AXI_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "M09_AXI_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "M09_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M09_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M09_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M09_AXI_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "M09_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M09_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M09_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M09_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M09_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M09_AXI_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "M09_AXI_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "M09_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M09_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M09_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M09_AXI_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "M09_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M09_AXI_rready" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+180
@@ -0,0 +1,180 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axis_data_fifo_0_0",
|
||||
"cell_name": "axis_data_fifo_0",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axis_aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_axis_aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+185
@@ -0,0 +1,185 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_axis_data_fifo_1_0",
|
||||
"cell_name": "axis_data_fifo_1",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"HAS_PROG_FULL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "32000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_axis_data_fifo_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000011011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "32000", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||
"s_axis_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axis_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"prog_full": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axis_aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_axis_aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1451
File diff suppressed because it is too large
Load Diff
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="54" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="53" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="48" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1600.000" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="54" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="MIO 22 .. 27" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="18" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 10 .. 11" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="18" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="54.563" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="54.563" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="54.563" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="54.563" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="1024 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.239" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="79.5025" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="60.536" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="71.7715" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="104.5365" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="70.676" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="59.1615" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="81.319" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="8 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J128M8 JP-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="14" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="30.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+195
@@ -0,0 +1,195 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_rst_ps7_0_50M_0",
|
||||
"cell_name": "rst_ps7_0_50M",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "13",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_a9_1_rst_ps7_0_50M_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "13" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+338
@@ -0,0 +1,338 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_smartconnect_0_0",
|
||||
"cell_name": "smartconnect_0",
|
||||
"component_reference": "xilinx.com:ip:smartconnect:1.0",
|
||||
"ip_revision": "20",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_a9_1_smartconnect_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADVANCED_PROPERTIES": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"TLM_COMPONENT_NAME": [ { "value": "design_a9_1_smartconnect_0_0", "resolve_type": "generated", "usage": "simulation.tlm" } ],
|
||||
"HAS_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "20" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"S00_AXI_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S00_AXI_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S00_AXI_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S01_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S01_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S01_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S01_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awlen": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"M00_AXI_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_awlock": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"M00_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_wlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_wvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arlen": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"M00_AXI_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_arlock": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"M00_AXI_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rready": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M00_AXI:S00_AXI:S01_AXI", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST.aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "16", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "128", "value_src": "user_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "S00_AXI_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "S00_AXI_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "S00_AXI_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "S00_AXI_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "S00_AXI_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "S00_AXI_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "S00_AXI_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "S00_AXI_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "S00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "S00_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "S00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "S00_AXI_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "S00_AXI_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "S00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "S00_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"S01_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "128", "value_src": "user_prop", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S01_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S01_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S01_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S01_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S01_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S01_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S01_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S01_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S01_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S01_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "S01_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S01_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S01_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S01_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S01_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "S01_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S01_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S01_AXI_bready" } ]
|
||||
}
|
||||
},
|
||||
"M00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "propagated", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "16", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_a9_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M00_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "M00_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "M00_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "M00_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "M00_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "M00_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "M00_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "M00_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "M00_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M00_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M00_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M00_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "M00_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "M00_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M00_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M00_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M00_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M00_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M00_AXI_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "M00_AXI_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "M00_AXI_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "M00_AXI_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "M00_AXI_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "M00_AXI_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "M00_AXI_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "M00_AXI_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "M00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M00_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M00_AXI_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "M00_AXI_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "M00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M00_AXI_rready" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+314
@@ -0,0 +1,314 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_a9_1_xlconcat_0_0",
|
||||
"cell_name": "xlconcat_0",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_a9_1_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
||||
"IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z010" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In2": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In3": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In4": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In5": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In6": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In7": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In8": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "8", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.755252",
|
||||
"Default View_TopLeft":"-136,687",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 5 -x 1740 -y 1480 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 5 -x 1740 -y 1500 -defaultsOSRD
|
||||
preplace port gpio0_0 -pg 1 -lvl 5 -x 1740 -y 480 -defaultsOSRD
|
||||
preplace port gpio0_1 -pg 1 -lvl 5 -x 1740 -y 500 -defaultsOSRD
|
||||
preplace port iic0 -pg 1 -lvl 5 -x 1740 -y 790 -defaultsOSRD
|
||||
preplace port m_axis_stim -pg 1 -lvl 5 -x 1740 -y 1250 -defaultsOSRD
|
||||
preplace port bram_stim -pg 1 -lvl 5 -x 1740 -y 80 -defaultsOSRD
|
||||
preplace port bram_eeg -pg 1 -lvl 5 -x 1740 -y 220 -defaultsOSRD
|
||||
preplace port bram_emg -pg 1 -lvl 5 -x 1740 -y 360 -defaultsOSRD
|
||||
preplace port iic1 -pg 1 -lvl 5 -x 1740 -y 1090 -defaultsOSRD
|
||||
preplace port bram_mems -pg 1 -lvl 5 -x 1740 -y 640 -defaultsOSRD
|
||||
preplace port bram_msg -pg 1 -lvl 5 -x 1740 -y 970 -defaultsOSRD
|
||||
preplace port s_axis_record -pg 1 -lvl 0 -x 0 -y 1730 -defaultsOSRD
|
||||
preplace port port-id_clk -pg 1 -lvl 5 -x 1740 -y 1560 -defaultsOSRD
|
||||
preplace port port-id_int0 -pg 1 -lvl 0 -x 0 -y 520 -defaultsOSRD
|
||||
preplace port port-id_int1 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
|
||||
preplace port port-id_int2 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
|
||||
preplace port port-id_s_axis_record_tfull -pg 1 -lvl 5 -x 1740 -y 1760 -defaultsOSRD
|
||||
preplace port port-id_int3 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
|
||||
preplace portBus rst_n -pg 1 -lvl 5 -x 1740 -y 1670 -defaultsOSRD
|
||||
preplace inst processing_system7_0 -pg 1 -lvl 4 -x 1460 -y 1530 -defaultsOSRD
|
||||
preplace inst axi_iic_0 -pg 1 -lvl 4 -x 1460 -y 810 -defaultsOSRD
|
||||
preplace inst axi_gpio_0 -pg 1 -lvl 4 -x 1460 -y 500 -defaultsOSRD
|
||||
preplace inst rst_ps7_0_50M -pg 1 -lvl 3 -x 960 -y 1530 -defaultsOSRD
|
||||
preplace inst xlconcat_0 -pg 1 -lvl 3 -x 960 -y 800 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 4 -x 1460 -y 80 -defaultsOSRD
|
||||
preplace inst axi_smc -pg 1 -lvl 1 -x 180 -y 670 -defaultsOSRD
|
||||
preplace inst axi_dma_0 -pg 1 -lvl 2 -x 560 -y 1130 -defaultsOSRD
|
||||
preplace inst axis_data_fifo_0 -pg 1 -lvl 4 -x 1460 -y 1250 -defaultsOSRD
|
||||
preplace inst axis_data_fifo_1 -pg 1 -lvl 4 -x 1460 -y 1750 -defaultsOSRD
|
||||
preplace inst smartconnect_0 -pg 1 -lvl 3 -x 960 -y 1320 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_1 -pg 1 -lvl 4 -x 1460 -y 220 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_2 -pg 1 -lvl 4 -x 1460 -y 360 -defaultsOSRD
|
||||
preplace inst axi_iic_1 -pg 1 -lvl 4 -x 1460 -y 1110 -defaultsOSRD
|
||||
preplace inst axi_dma_1 -pg 1 -lvl 2 -x 560 -y 1300 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_3 -pg 1 -lvl 4 -x 1460 -y 640 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_4 -pg 1 -lvl 4 -x 1460 -y 970 -defaultsOSRD
|
||||
preplace netloc axi_dma_0_mm2s_introut 1 2 1 770 840n
|
||||
preplace netloc axi_dma_1_s2mm_introut 1 2 1 780 860n
|
||||
preplace netloc axi_gpio_0_ip2intc_irpt 1 2 3 780 630 1260J 720 1670
|
||||
preplace netloc axi_iic_0_iic2intc_irpt 1 2 3 790 640 1190J 730 1670
|
||||
preplace netloc axi_iic_1_iic2intc_irpt 1 2 3 790 1230 1140J 1330 1670
|
||||
preplace netloc axis_data_fifo_1_prog_full 1 4 1 NJ 1760
|
||||
preplace netloc int0_1 1 0 3 NJ 520 NJ 520 760J
|
||||
preplace netloc int1_1 1 0 3 NJ 820 370J 810 760J
|
||||
preplace netloc int2_1 1 0 3 NJ 840 390J 820 NJ
|
||||
preplace netloc int3_1 1 0 3 NJ 880 NJ 880 NJ
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 5 40 1030 380 1030 760 1030 1220 1420 1690
|
||||
preplace netloc processing_system7_0_FCLK_RESET0_N 1 2 3 790 1410 NJ 1410 1660
|
||||
preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 0 5 30 1040 330 1040 750 1040 1180 1670 NJ
|
||||
preplace netloc xlconcat_0_dout 1 3 1 1190 800n
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 4 1 NJ 80
|
||||
preplace netloc axi_bram_ctrl_1_BRAM_PORTA 1 4 1 NJ 220
|
||||
preplace netloc axi_bram_ctrl_2_BRAM_PORTA 1 4 1 NJ 360
|
||||
preplace netloc axi_bram_ctrl_3_BRAM_PORTA 1 4 1 NJ 640
|
||||
preplace netloc axi_bram_ctrl_4_BRAM_PORTA 1 4 1 NJ 970
|
||||
preplace netloc axi_dma_0_M_AXIS_MM2S 1 2 2 720 1220 1210J
|
||||
preplace netloc axi_dma_0_M_AXI_MM2S 1 2 1 730 1100n
|
||||
preplace netloc axi_dma_1_M_AXI_S2MM 1 2 1 720 1280n
|
||||
preplace netloc axi_gpio_0_GPIO 1 4 1 NJ 480
|
||||
preplace netloc axi_gpio_0_GPIO2 1 4 1 NJ 500
|
||||
preplace netloc axi_iic_0_IIC 1 4 1 NJ 790
|
||||
preplace netloc axi_iic_1_IIC 1 4 1 NJ 1090
|
||||
preplace netloc axi_smc_M00_AXI 1 1 3 310 60 NJ 60 NJ
|
||||
preplace netloc axi_smc_M01_AXI 1 1 3 330 480 NJ 480 NJ
|
||||
preplace netloc axi_smc_M02_AXI 1 1 3 320 200 NJ 200 NJ
|
||||
preplace netloc axi_smc_M03_AXI 1 1 3 340 340 NJ 340 NJ
|
||||
preplace netloc axi_smc_M04_AXI 1 1 3 N 660 NJ 660 1140J
|
||||
preplace netloc axi_smc_M05_AXI 1 1 3 380 610 NJ 610 1260J
|
||||
preplace netloc axi_smc_M06_AXI 1 1 1 350 700n
|
||||
preplace netloc axi_smc_M07_AXI 1 1 1 340 720n
|
||||
preplace netloc axi_smc_M08_AXI 1 1 3 370 600 NJ 600 1250J
|
||||
preplace netloc axi_smc_M09_AXI 1 1 3 390 620 NJ 620 1240J
|
||||
preplace netloc axis_data_fifo_0_M_AXIS 1 4 1 NJ 1250
|
||||
preplace netloc axis_data_fifo_1_M_AXIS 1 1 4 400 650 NJ 650 1230J 890 1680
|
||||
preplace netloc processing_system7_0_DDR 1 4 1 NJ 1480
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 4 1 NJ 1500
|
||||
preplace netloc processing_system7_0_M_AXI_GP0 1 0 5 50 1020 NJ 1020 NJ 1020 1200J 1340 1670
|
||||
preplace netloc s_axis_record_1 1 0 4 NJ 1730 NJ 1730 NJ 1730 NJ
|
||||
preplace netloc smartconnect_0_M00_AXI 1 3 1 1130 1320n
|
||||
levelinfo -pg 1 0 180 560 960 1460 1740
|
||||
pagesize -pg 1 -db -bbox -sgen -150 0 1930 1830
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"54",
|
||||
"da_board_cnt":"17",
|
||||
"da_bram_cntlr_cnt":"3",
|
||||
"da_clkrst_cnt":"35",
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
Reference in New Issue
Block a user