上传PL工程
This commit is contained in:
chenmin
@@ -0,0 +1,172 @@
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc id:1} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc id:2} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc id:3} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc id:4} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc id:5} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc rfile:../../../c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc id:6} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T15 [get_ports {eeg_ads1299_spi_cs[0]}]
|
||||
set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R19 [get_ports {eeg_ads1299_spi_cs[1]}]
|
||||
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y18 [get_ports {eeg_ads1299_spi_cs[2]}]
|
||||
set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W18 [get_ports {eeg_ads1299_spi_cs[3]}]
|
||||
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V20 [get_ports {eeg_ads1299_spi_cs[4]}]
|
||||
set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W20 [get_ports {eeg_ads1299_spi_cs[5]}]
|
||||
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R16 [get_ports {eeg_ads1299_spi_cs[6]}]
|
||||
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R17 [get_ports {eeg_ads1299_spi_cs[7]}]
|
||||
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P18 [get_ports {eeg_ads1299_spi_sclk[0]}]
|
||||
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V18 [get_ports {eeg_ads1299_spi_sclk[1]}]
|
||||
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P20 [get_ports {eeg_ads1299_spi_sclk[2]}]
|
||||
set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V16 [get_ports {eeg_ads1299_spi_sclk[3]}]
|
||||
set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T14 [get_ports {eeg_ads1299_spi_mosi[0]}]
|
||||
set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y19 [get_ports {eeg_ads1299_spi_mosi[1]}]
|
||||
set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U20 [get_ports {eeg_ads1299_spi_mosi[2]}]
|
||||
set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R18 [get_ports {eeg_ads1299_spi_mosi[3]}]
|
||||
set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P19 [get_ports {eeg_ads1299_spi_miso[0]}]
|
||||
set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W19 [get_ports {eeg_ads1299_spi_miso[1]}]
|
||||
set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T20 [get_ports {eeg_ads1299_spi_miso[2]}]
|
||||
set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V17 [get_ports {eeg_ads1299_spi_miso[3]}]
|
||||
set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN N18 [get_ports {eeg_ads1299_drdy_n[0]}]
|
||||
set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T17 [get_ports {eeg_ads1299_drdy_n[1]}]
|
||||
set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN N20 [get_ports {eeg_ads1299_drdy_n[2]}]
|
||||
set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W16 [get_ports {eeg_ads1299_drdy_n[3]}]
|
||||
set_property src_info {type:XDC file:1 line:109 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T16 [get_ports {eeg_ads1299_start}]
|
||||
set_property src_info {type:XDC file:2 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN K17 [get_ports {emg_ads1299_spi_cs}]
|
||||
set_property src_info {type:XDC file:2 line:9 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L17 [get_ports {emg_ads1299_spi_sclk}]
|
||||
set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN K18 [get_ports {emg_ads1299_spi_mosi}]
|
||||
set_property src_info {type:XDC file:2 line:19 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H16 [get_ports {emg_ads1299_spi_miso}]
|
||||
set_property src_info {type:XDC file:2 line:24 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L16 [get_ports {emg_ads1299_drdy_n}]
|
||||
set_property src_info {type:XDC file:2 line:29 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H17 [get_ports {emg_ads1299_start}]
|
||||
set_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H18 [get_ports {emg_ads1299_reset_n}]
|
||||
set_property src_info {type:XDC file:2 line:39 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J18 [get_ports {emg_ads1299_pwdn_n}]
|
||||
set_property src_info {type:XDC file:3 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN B19 [get_ports adg1414_spi_sync]
|
||||
set_property src_info {type:XDC file:3 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN E17 [get_ports adg1414_spi_sclk]
|
||||
set_property src_info {type:XDC file:3 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN A20 [get_ports adg1414_spi_mosi]
|
||||
set_property src_info {type:XDC file:3 line:16 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN D18 [get_ports adg1414_spi_miso]
|
||||
set_property src_info {type:XDC file:3 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN F20 [get_ports accel_spi_cs]
|
||||
set_property src_info {type:XDC file:3 line:25 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G17 [get_ports accel_spi_sclk]
|
||||
set_property src_info {type:XDC file:3 line:29 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J20 [get_ports accel_spi_mosi]
|
||||
set_property src_info {type:XDC file:3 line:33 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G18 [get_ports accel_spi_miso]
|
||||
set_property src_info {type:XDC file:3 line:37 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN H20 [get_ports accel_int0]
|
||||
set_property src_info {type:XDC file:3 line:41 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G19 [get_ports accel_int1]
|
||||
set_property src_info {type:XDC file:3 line:46 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN E19 [get_ports z_scl]
|
||||
set_property src_info {type:XDC file:3 line:51 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN F16 [get_ports z_sda]
|
||||
set_property src_info {type:XDC file:4 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN C20 [get_ports led_state]
|
||||
set_property src_info {type:XDC file:4 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN B20 [get_ports led_wifi]
|
||||
set_property src_info {type:XDC file:4 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN D20 [get_ports led_stim]
|
||||
set_property src_info {type:XDC file:4 line:17 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN K14 [get_ports {trigger_i[0]}]
|
||||
set_property src_info {type:XDC file:4 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G15 [get_ports {trigger_i[1]}]
|
||||
set_property src_info {type:XDC file:4 line:25 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN N15 [get_ports {trigger_i[2]}]
|
||||
set_property src_info {type:XDC file:4 line:29 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN N16 [get_ports {trigger_o[0]}]
|
||||
set_property src_info {type:XDC file:4 line:34 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M14 [get_ports {usb_power_check}]
|
||||
set_property src_info {type:XDC file:4 line:39 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN G14 [get_ports {led_pl[0]}]
|
||||
set_property src_info {type:XDC file:4 line:43 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN J15 [get_ports {led_pl[1]}]
|
||||
set_property src_info {type:XDC file:5 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M17 [get_ports gauge_scl]
|
||||
set_property src_info {type:XDC file:5 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M20 [get_ports gauge_sda]
|
||||
set_property src_info {type:XDC file:5 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN K16 [get_ports gauge_indicate]
|
||||
set_property src_info {type:XDC file:5 line:17 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U15 [get_ports power_on_rsh2116_a]
|
||||
set_property src_info {type:XDC file:5 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W15 [get_ports power_on_rsh2116_d]
|
||||
set_property src_info {type:XDC file:5 line:25 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P15 [get_ports power_on_ads1299]
|
||||
set_property src_info {type:XDC file:5 line:29 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN L19 [get_ports power_on_z]
|
||||
set_property src_info {type:XDC file:5 line:33 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN D19 [get_ports power_sw_z]
|
||||
set_property src_info {type:XDC file:6 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T19 [get_ports {rsh2116_enable[0]}]
|
||||
set_property src_info {type:XDC file:6 line:8 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y14 [get_ports {rsh2116_enable[1]}]
|
||||
set_property src_info {type:XDC file:6 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y16 [get_ports {rsh2116_enable[2]}]
|
||||
set_property src_info {type:XDC file:6 line:16 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T12 [get_ports {rsh2116_enable[3]}]
|
||||
set_property src_info {type:XDC file:6 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U18 [get_ports {rsh2116_spi_cs[0]}]
|
||||
set_property src_info {type:XDC file:6 line:25 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V13 [get_ports {rsh2116_spi_cs[1]}]
|
||||
set_property src_info {type:XDC file:6 line:29 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U14 [get_ports {rsh2116_spi_cs[2]}]
|
||||
set_property src_info {type:XDC file:6 line:33 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T11 [get_ports {rsh2116_spi_cs[3]}]
|
||||
set_property src_info {type:XDC file:6 line:38 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U19 [get_ports {rsh2116_spi_sclk[0]}]
|
||||
set_property src_info {type:XDC file:6 line:42 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V12 [get_ports {rsh2116_spi_sclk[1]}]
|
||||
set_property src_info {type:XDC file:6 line:46 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN V15 [get_ports {rsh2116_spi_sclk[2]}]
|
||||
set_property src_info {type:XDC file:6 line:50 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN T10 [get_ports {rsh2116_spi_sclk[3]}]
|
||||
set_property src_info {type:XDC file:6 line:55 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U17 [get_ports {rsh2116_spi_mosi[0]}]
|
||||
set_property src_info {type:XDC file:6 line:59 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U12 [get_ports {rsh2116_spi_mosi[1]}]
|
||||
set_property src_info {type:XDC file:6 line:63 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W14 [get_ports {rsh2116_spi_mosi[2]}]
|
||||
set_property src_info {type:XDC file:6 line:67 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R14 [get_ports {rsh2116_spi_mosi[3]}]
|
||||
set_property src_info {type:XDC file:6 line:72 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y17 [get_ports {rsh2116_spi_miso[0]}]
|
||||
set_property src_info {type:XDC file:6 line:76 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W13 [get_ports {rsh2116_spi_miso[1]}]
|
||||
set_property src_info {type:XDC file:6 line:80 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN U13 [get_ports {rsh2116_spi_miso[2]}]
|
||||
set_property src_info {type:XDC file:6 line:84 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P14 [get_ports {rsh2116_spi_miso[3]}]
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="wenlibin" Host="840-5CG14025H4" Pid="55560" HostCore="8" HostMemory="034024464384">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,324 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/c64pro_top.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "synth_1" START { ROLLUP_AUTO }
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z010clg400-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/projects/vivadoPrj/c64_pro/c64_pro.cache/wt [current_project]
|
||||
set_property parent.project_path D:/projects/vivadoPrj/c64_pro/c64_pro.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/projects/vivadoPrj/c64_pro/c64_pro.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_verilog -library xil_defaultlib {
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/accel/accel_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/channel_switch.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/debouncing.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/emg/emg_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/led_ctrl.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/run_time.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_config.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v
|
||||
D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/c64pro_top.v
|
||||
}
|
||||
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_ooc.xdc]
|
||||
|
||||
add_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/bd_6e35_arinsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/bd_6e35_rinsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/bd_6e35_awinsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/bd_6e35_winsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/bd_6e35_binsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/bd_6e35_aroutsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/bd_6e35_routsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/bd_6e35_awoutsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/bd_6e35_woutsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/bd_6e35_boutsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/bd_6e35_arni_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/bd_6e35_rni_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/bd_6e35_awni_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/bd_6e35_wni_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/bd_6e35_bni_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/bd_6e35_s00a2s_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/bd_6e35_sarn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/bd_6e35_srn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/bd_6e35_sawn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/bd_6e35_swn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/bd_6e35_sbn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/bd_6e35_m00s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/bd_6e35_m00arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/bd_6e35_m00rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/bd_6e35_m00awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/bd_6e35_m00wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/bd_6e35_m00bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/bd_6e35_m01s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/bd_6e35_m01arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/bd_6e35_m01rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/bd_6e35_m01awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/bd_6e35_m01wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/bd_6e35_m01bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/bd_6e35_m02s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/bd_6e35_m02arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/bd_6e35_m02rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/bd_6e35_m02awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/bd_6e35_m02wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/bd_6e35_m02bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/bd_6e35_m03s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/bd_6e35_m03arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/bd_6e35_m03rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/bd_6e35_m03awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/bd_6e35_m03wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/bd_6e35_m03bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/bd_6e35_m04s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/bd_6e35_m04arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/bd_6e35_m04rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/bd_6e35_m04awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/bd_6e35_m04wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/bd_6e35_m04bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_61/bd_6e35_m05s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_62/bd_6e35_m05arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_63/bd_6e35_m05rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_64/bd_6e35_m05awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_65/bd_6e35_m05wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_66/bd_6e35_m05bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_68/bd_6e35_m06s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_69/bd_6e35_m06arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_70/bd_6e35_m06rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_71/bd_6e35_m06awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_72/bd_6e35_m06wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_73/bd_6e35_m06bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_75/bd_6e35_m07s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_76/bd_6e35_m07arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_77/bd_6e35_m07rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_78/bd_6e35_m07awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_79/bd_6e35_m07wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_80/bd_6e35_m07bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_82/bd_6e35_m08s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_83/bd_6e35_m08arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_84/bd_6e35_m08rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_85/bd_6e35_m08awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_86/bd_6e35_m08wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_87/bd_6e35_m08bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_89/bd_6e35_m09s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_90/bd_6e35_m09arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_91/bd_6e35_m09rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_92/bd_6e35_m09awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_93/bd_6e35_m09wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_94/bd_6e35_m09bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/bd_962a_arsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/bd_962a_rsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/bd_962a_awsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/bd_962a_wsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/bd_962a_bsw_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/bd_962a_s00a2s_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/bd_962a_sarn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/bd_962a_srn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/bd_962a_s01a2s_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/bd_962a_sawn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/bd_962a_swn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/bd_962a_sbn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_20/bd_962a_m00s2a_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_21/bd_962a_m00arn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_22/bd_962a_m00rn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/bd_962a_m00awn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/bd_962a_m00wn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/bd_962a_m00bn_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc]
|
||||
|
||||
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32.xci
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_ooc.xdc]
|
||||
|
||||
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc]
|
||||
|
||||
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16.xci
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_ooc.xdc]
|
||||
|
||||
read_ip -quiet D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci
|
||||
set_property used_in_implementation false [get_files -all d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
||||
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
||||
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
||||
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
|
||||
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
|
||||
|
||||
read_xdc D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc
|
||||
set_property used_in_implementation false [get_files D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
|
||||
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top c64pro_top -part xc7z010clg400-2
|
||||
OPTRACE "synth_design" END { }
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef c64pro_top.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "synth_1" END { }
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,208 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
| Date : Sun Aug 4 13:40:31 2024
|
||||
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
|
||||
| Design : c64pro_top
|
||||
| Device : xc7z010clg400-2
|
||||
| Speed File : -2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice LUTs* | 6173 | 0 | 0 | 17600 | 35.07 |
|
||||
| LUT as Logic | 6173 | 0 | 0 | 17600 | 35.07 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
|
||||
| Slice Registers | 11236 | 0 | 0 | 35200 | 31.92 |
|
||||
| Register as Flip Flop | 11108 | 0 | 0 | 35200 | 31.56 |
|
||||
| Register as Latch | 128 | 0 | 0 | 35200 | 0.36 |
|
||||
| F7 Muxes | 997 | 0 | 0 | 8800 | 11.33 |
|
||||
| F8 Muxes | 452 | 0 | 0 | 4400 | 10.27 |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 366 | Yes | - | Set |
|
||||
| 10838 | Yes | - | Reset |
|
||||
| 32 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 76 | 0 | 0 | 100 | 76.00 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+-------+---------------------+
|
||||
| FDCE | 10710 | Flop & Latch |
|
||||
| LUT6 | 3858 | LUT |
|
||||
| MUXF7 | 997 | MuxFx |
|
||||
| LUT3 | 855 | LUT |
|
||||
| LUT5 | 846 | LUT |
|
||||
| LUT2 | 841 | LUT |
|
||||
| LUT4 | 672 | LUT |
|
||||
| MUXF8 | 452 | MuxFx |
|
||||
| FDPE | 366 | Flop & Latch |
|
||||
| CARRY4 | 274 | CarryLogic |
|
||||
| LUT1 | 133 | LUT |
|
||||
| LDCE | 128 | Flop & Latch |
|
||||
| OBUF | 56 | IO |
|
||||
| FDSE | 32 | Flop & Latch |
|
||||
| IBUF | 20 | IO |
|
||||
| OBUFT | 4 | IO |
|
||||
| BUFG | 4 | Clock |
|
||||
+----------+-------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+------------------------------------+------+
|
||||
| Ref Name | Used |
|
||||
+------------------------------------+------+
|
||||
| mult_gen_au8_bu9_p8 | 4 |
|
||||
| axis_data_fifo_w32_d32 | 4 |
|
||||
| design_a9_1_smartconnect_0_0 | 1 |
|
||||
| design_a9_1_rst_ps7_0_50M_0 | 1 |
|
||||
| design_a9_1_processing_system7_0_0 | 1 |
|
||||
| design_a9_1_axis_data_fifo_1_0 | 1 |
|
||||
| design_a9_1_axis_data_fifo_0_0 | 1 |
|
||||
| design_a9_1_axi_smc_0 | 1 |
|
||||
| design_a9_1_axi_iic_1_0 | 1 |
|
||||
| design_a9_1_axi_iic_0_0 | 1 |
|
||||
| design_a9_1_axi_gpio_0_0 | 1 |
|
||||
| design_a9_1_axi_dma_1_0 | 1 |
|
||||
| design_a9_1_axi_dma_0_0 | 1 |
|
||||
| design_a9_1_axi_bram_ctrl_4_0 | 1 |
|
||||
| design_a9_1_axi_bram_ctrl_3_0 | 1 |
|
||||
| design_a9_1_axi_bram_ctrl_2_0 | 1 |
|
||||
| design_a9_1_axi_bram_ctrl_1_0 | 1 |
|
||||
| design_a9_1_axi_bram_ctrl_0_0 | 1 |
|
||||
| dds_stim_16ch | 1 |
|
||||
| axis_data_fifo_w8_d128 | 1 |
|
||||
| axis_data_fifo_w32_d16 | 1 |
|
||||
+------------------------------------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# XDC: new/c64pro_pins_ads1299.xdc
|
||||
|
||||
# XDC: new/c64pro_pins_ads1299_emg.xdc
|
||||
|
||||
# XDC: new/c64pro_pins_ic.xdc
|
||||
|
||||
# XDC: new/c64pro_pins_misc.xdc
|
||||
|
||||
# XDC: new/c64pro_pins_pm.xdc
|
||||
|
||||
# XDC: new/c64pro_pins_rsh2116.xdc
|
||||
|
||||
# IP: ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==mult_gen_au8_bu9_p8 || ORIG_REF_NAME==mult_gen_au8_bu9_p8} -quiet] -quiet
|
||||
|
||||
# Block Designs: bd/design_a9_1/design_a9_1.bd
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1 || ORIG_REF_NAME==design_a9_1} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_processing_system7_0_0 || ORIG_REF_NAME==design_a9_1_processing_system7_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_iic_0_0 || ORIG_REF_NAME==design_a9_1_axi_iic_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_gpio_0_0 || ORIG_REF_NAME==design_a9_1_axi_gpio_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_rst_ps7_0_50M_0 || ORIG_REF_NAME==design_a9_1_rst_ps7_0_50M_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/design_a9_1_xlconcat_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_xlconcat_0_0 || ORIG_REF_NAME==design_a9_1_xlconcat_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_0_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_smc_0 || ORIG_REF_NAME==design_a9_1_axi_smc_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_0_0 || ORIG_REF_NAME==design_a9_1_axi_dma_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_0_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axis_data_fifo_1_0 || ORIG_REF_NAME==design_a9_1_axis_data_fifo_1_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_smartconnect_0_0 || ORIG_REF_NAME==design_a9_1_smartconnect_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_1_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_1_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_2_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_2_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_iic_1_0 || ORIG_REF_NAME==design_a9_1_axi_iic_1_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_dma_1_0 || ORIG_REF_NAME==design_a9_1_axi_dma_1_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_3_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_3_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_a9_1_axi_bram_ctrl_4_0 || ORIG_REF_NAME==design_a9_1_axi_bram_ctrl_4_0} -quiet] -quiet
|
||||
|
||||
# XDC: d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/design_a9_1_ooc.xdc
|
||||
@@ -0,0 +1,343 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-2" LaunchTime="1722749885">
|
||||
<File Type="PA-TCL" Name="c64pro_top.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="c64pro_top_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="c64pro_top_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="c64pro_top.vds"/>
|
||||
<File Type="RDS-UTIL" Name="c64pro_top_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="c64pro_top_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="c64pro_top.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="c64pro_top_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="c64pro_top_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/accel/accel_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/switch/adg1414_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/utils/breath_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/switch/channel_switch.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/cnv_res_collect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/utils/debouncing.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_config.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_upload.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/emg/emg_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/pl_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/utils/pwm_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/sine_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/utils/spi_full_duplex_master.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_event_collect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/stim_monitor.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_arrange.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_distribute.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_timer.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_config.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_detection.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_protocol_intan.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_protocol_ql.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_sort.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/rtl/c64pro_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="c64pro_top"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ads1299.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ads1299_emg.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_misc.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_pm.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_rsh2116.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d32"/>
|
||||
<BlockFileSet Type="BlockSrcs" Name="dds_stim_16ch"/>
|
||||
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w32_d16"/>
|
||||
<BlockFileSet Type="BlockSrcs" Name="axis_data_fifo_w8_d128"/>
|
||||
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_axi_gpio_0_0"/>
|
||||
<BlockFileSet Type="BlockSrcs" Name="design_a9_1_processing_system7_0_0"/>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,10 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log c64pro_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
|
||||
@@ -0,0 +1,37 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2023.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log c64pro_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,44 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/Vitis/2023.1/bin;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2023.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2023.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log c64pro_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
|
||||
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.1 (64-bit)
|
||||
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
||||
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
||||
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
|
||||
# Start of session at: Sun Aug 4 13:38:09 2024
|
||||
# Process ID: 52932
|
||||
# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1
|
||||
# Command line: vivado.exe -log c64pro_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
|
||||
# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/c64pro_top.vds
|
||||
# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1\vivado.jou
|
||||
# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB
|
||||
#-----------------------------------------------------------
|
||||
source c64pro_top.tcl -notrace
|
||||
Binary file not shown.
Reference in New Issue
Block a user