上传PL工程
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of AMD and is protected under U.S. and international copyright
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// and other intellectual property laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// AMD, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) AMD shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or AMD had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// AMD products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of AMD products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:dds_compiler:6.0
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// IP Revision: 22
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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dds_stim_16ch your_instance_name (
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.aclk(aclk), // input wire aclk
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.aclken(aclken), // input wire aclken
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.aresetn(aresetn), // input wire aresetn
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.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
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.s_axis_config_tdata(s_axis_config_tdata), // input wire [63 : 0] s_axis_config_tdata
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.s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast
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.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
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.m_axis_data_tdata(m_axis_data_tdata), // output wire [15 : 0] m_axis_data_tdata
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.m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid
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.m_axis_phase_tdata(m_axis_phase_tdata), // output wire [31 : 0] m_axis_phase_tdata
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.event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing
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.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file dds_stim_16ch.v when simulating
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// the core, dds_stim_16ch. When compiling the wrapper file, be sure to
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// reference the Verilog simulation library.
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@@ -0,0 +1,98 @@
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of AMD and is protected under U.S. and international copyright
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-- and other intellectual property laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- AMD, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) AMD shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or AMD had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- AMD products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of AMD products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- DO NOT MODIFY THIS FILE.
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-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
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-- IP Revision: 22
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-- The following code must appear in the VHDL architecture header.
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT dds_stim_16ch
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PORT (
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aclk : IN STD_LOGIC;
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aclken : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_config_tvalid : IN STD_LOGIC;
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s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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s_axis_config_tlast : IN STD_LOGIC;
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m_axis_data_tvalid : OUT STD_LOGIC;
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m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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m_axis_phase_tvalid : OUT STD_LOGIC;
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m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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event_s_config_tlast_missing : OUT STD_LOGIC;
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event_s_config_tlast_unexpected : OUT STD_LOGIC
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);
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : dds_stim_16ch
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PORT MAP (
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aclk => aclk,
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aclken => aclken,
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aresetn => aresetn,
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s_axis_config_tvalid => s_axis_config_tvalid,
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s_axis_config_tdata => s_axis_config_tdata,
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s_axis_config_tlast => s_axis_config_tlast,
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m_axis_data_tvalid => m_axis_data_tvalid,
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m_axis_data_tdata => m_axis_data_tdata,
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m_axis_phase_tvalid => m_axis_phase_tvalid,
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m_axis_phase_tdata => m_axis_phase_tdata,
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event_s_config_tlast_missing => event_s_config_tlast_missing,
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event_s_config_tlast_unexpected => event_s_config_tlast_unexpected
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);
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-- INST_TAG_END ------ End INSTANTIATION Template ---------
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-- You must compile the wrapper file dds_stim_16ch.vhd when simulating
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-- the core, dds_stim_16ch. When compiling the wrapper file, be sure to
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-- reference the VHDL simulation library.
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
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// Date : Thu Aug 17 17:22:27 2023
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// Host : wlbpc running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub
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// d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_stub.v
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// Design : dds_stim_16ch
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z010clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "dds_compiler_v6_0_22,Vivado 2023.1.1" *)
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module dds_stim_16ch(aclk, aclken, aresetn, s_axis_config_tvalid,
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s_axis_config_tdata, s_axis_config_tlast, m_axis_data_tvalid, m_axis_data_tdata,
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m_axis_phase_tvalid, m_axis_phase_tdata, event_s_config_tlast_missing,
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event_s_config_tlast_unexpected)
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/* synthesis syn_black_box black_box_pad_pin="aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected" */
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/* synthesis syn_force_seq_prim="aclk" */;
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input aclk /* synthesis syn_isclock = 1 */;
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input aclken;
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input aresetn;
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input s_axis_config_tvalid;
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input [63:0]s_axis_config_tdata;
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input s_axis_config_tlast;
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output m_axis_data_tvalid;
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output [15:0]m_axis_data_tdata;
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output m_axis_phase_tvalid;
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output [31:0]m_axis_phase_tdata;
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output event_s_config_tlast_missing;
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output event_s_config_tlast_unexpected;
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endmodule
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@@ -0,0 +1,42 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
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-- Date : Thu Aug 17 17:22:27 2023
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-- Host : wlbpc running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub
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-- d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_stub.vhdl
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-- Design : dds_stim_16ch
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z010clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity dds_stim_16ch is
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Port (
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aclk : in STD_LOGIC;
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aclken : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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s_axis_config_tvalid : in STD_LOGIC;
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s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
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s_axis_config_tlast : in STD_LOGIC;
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m_axis_data_tvalid : out STD_LOGIC;
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m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
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m_axis_phase_tvalid : out STD_LOGIC;
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m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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event_s_config_tlast_missing : out STD_LOGIC;
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event_s_config_tlast_unexpected : out STD_LOGIC
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);
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end dds_stim_16ch;
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architecture stub of dds_stim_16ch is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "aclk,aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "dds_compiler_v6_0_22,Vivado 2023.1.1";
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begin
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end;
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