上传PL工程
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@@ -0,0 +1,72 @@
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
// IP Revision: 10
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
axis_data_fifo_w32_d16 your_instance_name (
|
||||
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
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||||
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
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||||
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
|
||||
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
|
||||
.s_axis_tdata(s_axis_tdata), // input wire [31 : 0] s_axis_tdata
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||||
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
|
||||
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
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||||
.m_axis_tdata(m_axis_tdata) // output wire [31 : 0] m_axis_tdata
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||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file axis_data_fifo_w32_d16.v when simulating
|
||||
// the core, axis_data_fifo_w32_d16. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,90 @@
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||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
-- IP Revision: 10
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
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||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT axis_data_fifo_w32_d16
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PORT (
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s_axis_aresetn : IN STD_LOGIC;
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||||
s_axis_aclk : IN STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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||||
m_axis_tvalid : OUT STD_LOGIC;
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||||
m_axis_tready : IN STD_LOGIC;
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||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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||||
);
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||||
END COMPONENT;
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||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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||||
your_instance_name : axis_data_fifo_w32_d16
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||||
PORT MAP (
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||||
s_axis_aresetn => s_axis_aresetn,
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||||
s_axis_aclk => s_axis_aclk,
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||||
s_axis_tvalid => s_axis_tvalid,
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||||
s_axis_tready => s_axis_tready,
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||||
s_axis_tdata => s_axis_tdata,
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||||
m_axis_tvalid => m_axis_tvalid,
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||||
m_axis_tready => m_axis_tready,
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||||
m_axis_tdata => m_axis_tdata
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||||
);
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||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file axis_data_fifo_w32_d16.vhd when simulating
|
||||
-- the core, axis_data_fifo_w32_d16. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,30 @@
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
// Date : Wed Dec 27 21:08:27 2023
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode synth_stub
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||||
// d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_stub.v
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||||
// Design : axis_data_fifo_w32_d16
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||||
// Purpose : Stub declaration of top-level module interface
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||||
// Device : xc7z010clg400-2
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||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
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||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
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module axis_data_fifo_w32_d16(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
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s_axis_tready, s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
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||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */
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||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
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||||
input s_axis_aresetn;
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||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
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||||
input s_axis_tvalid;
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||||
output s_axis_tready;
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||||
input [31:0]s_axis_tdata;
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||||
output m_axis_tvalid;
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||||
input m_axis_tready;
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||||
output [31:0]m_axis_tdata;
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||||
endmodule
|
||||
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Dec 27 21:08:27 2023
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_stub.vhdl
|
||||
-- Design : axis_data_fifo_w32_d16
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
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||||
entity axis_data_fifo_w32_d16 is
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||||
Port (
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||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end axis_data_fifo_w32_d16;
|
||||
|
||||
architecture stub of axis_data_fifo_w32_d16 is
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||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]";
|
||||
attribute X_CORE_INFO : string;
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||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,74 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
// IP Revision: 10
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
axis_data_fifo_w32_d32 your_instance_name (
|
||||
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
|
||||
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
|
||||
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
|
||||
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
|
||||
.s_axis_tdata(s_axis_tdata), // input wire [31 : 0] s_axis_tdata
|
||||
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
|
||||
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
|
||||
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
|
||||
.m_axis_tdata(m_axis_tdata), // output wire [31 : 0] m_axis_tdata
|
||||
.m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file axis_data_fifo_w32_d32.v when simulating
|
||||
// the core, axis_data_fifo_w32_d32. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
-- IP Revision: 10
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT axis_data_fifo_w32_d32
|
||||
PORT (
|
||||
s_axis_aresetn : IN STD_LOGIC;
|
||||
s_axis_aclk : IN STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : axis_data_fifo_w32_d32
|
||||
PORT MAP (
|
||||
s_axis_aresetn => s_axis_aresetn,
|
||||
s_axis_aclk => s_axis_aclk,
|
||||
s_axis_tvalid => s_axis_tvalid,
|
||||
s_axis_tready => s_axis_tready,
|
||||
s_axis_tdata => s_axis_tdata,
|
||||
s_axis_tlast => s_axis_tlast,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tready => m_axis_tready,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tlast => m_axis_tlast
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file axis_data_fifo_w32_d32.vhd when simulating
|
||||
-- the core, axis_data_fifo_w32_d32. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
|
||||
// Date : Thu Aug 10 15:50:34 2023
|
||||
// Host : wlbpc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v
|
||||
// Design : axis_data_fifo_w32_d32
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1.1" *)
|
||||
module axis_data_fifo_w32_d32(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tlast, m_axis_tvalid, m_axis_tready, m_axis_tdata,
|
||||
m_axis_tlast)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [31:0]s_axis_tdata;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [31:0]m_axis_tdata;
|
||||
output m_axis_tlast;
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
|
||||
-- Date : Thu Aug 10 15:50:34 2023
|
||||
-- Host : wlbpc running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.vhdl
|
||||
-- Design : axis_data_fifo_w32_d32
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_data_fifo_w32_d32 is
|
||||
Port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_tlast : out STD_LOGIC
|
||||
);
|
||||
|
||||
end axis_data_fifo_w32_d32;
|
||||
|
||||
architecture stub of axis_data_fifo_w32_d32 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,74 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
// IP Revision: 10
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
axis_data_fifo_w8_d128 your_instance_name (
|
||||
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
|
||||
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
|
||||
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
|
||||
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
|
||||
.s_axis_tdata(s_axis_tdata), // input wire [7 : 0] s_axis_tdata
|
||||
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
|
||||
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
|
||||
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
|
||||
.m_axis_tdata(m_axis_tdata), // output wire [7 : 0] m_axis_tdata
|
||||
.m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file axis_data_fifo_w8_d128.v when simulating
|
||||
// the core, axis_data_fifo_w8_d128. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:axis_data_fifo:2.0
|
||||
-- IP Revision: 10
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT axis_data_fifo_w8_d128
|
||||
PORT (
|
||||
s_axis_aresetn : IN STD_LOGIC;
|
||||
s_axis_aclk : IN STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : axis_data_fifo_w8_d128
|
||||
PORT MAP (
|
||||
s_axis_aresetn => s_axis_aresetn,
|
||||
s_axis_aclk => s_axis_aclk,
|
||||
s_axis_tvalid => s_axis_tvalid,
|
||||
s_axis_tready => s_axis_tready,
|
||||
s_axis_tdata => s_axis_tdata,
|
||||
s_axis_tlast => s_axis_tlast,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tready => m_axis_tready,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tlast => m_axis_tlast
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file axis_data_fifo_w8_d128.vhd when simulating
|
||||
-- the core, axis_data_fifo_w8_d128. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Mar 29 11:59:39 2024
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.v
|
||||
// Design : axis_data_fifo_w8_d128
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
|
||||
module axis_data_fifo_w8_d128(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tlast, m_axis_tvalid, m_axis_tready, m_axis_tdata,
|
||||
m_axis_tlast)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [7:0]s_axis_tdata;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [7:0]m_axis_tdata;
|
||||
output m_axis_tlast;
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Fri Mar 29 11:59:39 2024
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_stub.vhdl
|
||||
-- Design : axis_data_fifo_w8_d128
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_data_fifo_w8_d128 is
|
||||
Port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_tlast : out STD_LOGIC
|
||||
);
|
||||
|
||||
end axis_data_fifo_w8_d128;
|
||||
|
||||
architecture stub of axis_data_fifo_w8_d128 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,76 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
// IP Revision: 22
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
dds_stim_16ch your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.aclken(aclken), // input wire aclken
|
||||
.aresetn(aresetn), // input wire aresetn
|
||||
.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata(s_axis_config_tdata), // input wire [63 : 0] s_axis_config_tdata
|
||||
.s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata), // output wire [15 : 0] m_axis_data_tdata
|
||||
.m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid
|
||||
.m_axis_phase_tdata(m_axis_phase_tdata), // output wire [31 : 0] m_axis_phase_tdata
|
||||
.event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing
|
||||
.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file dds_stim_16ch.v when simulating
|
||||
// the core, dds_stim_16ch. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
-- IP Revision: 22
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT dds_stim_16ch
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : dds_stim_16ch
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => aclken,
|
||||
aresetn => aresetn,
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
s_axis_config_tlast => s_axis_config_tlast,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata,
|
||||
m_axis_phase_tvalid => m_axis_phase_tvalid,
|
||||
m_axis_phase_tdata => m_axis_phase_tdata,
|
||||
event_s_config_tlast_missing => event_s_config_tlast_missing,
|
||||
event_s_config_tlast_unexpected => event_s_config_tlast_unexpected
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file dds_stim_16ch.vhd when simulating
|
||||
-- the core, dds_stim_16ch. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
|
||||
// Date : Thu Aug 17 17:22:27 2023
|
||||
// Host : wlbpc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_stub.v
|
||||
// Design : dds_stim_16ch
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_22,Vivado 2023.1.1" *)
|
||||
module dds_stim_16ch(aclk, aclken, aresetn, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, s_axis_config_tlast, m_axis_data_tvalid, m_axis_data_tdata,
|
||||
m_axis_phase_tvalid, m_axis_phase_tdata, event_s_config_tlast_missing,
|
||||
event_s_config_tlast_unexpected)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aclken;
|
||||
input aresetn;
|
||||
input s_axis_config_tvalid;
|
||||
input [63:0]s_axis_config_tdata;
|
||||
input s_axis_config_tlast;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
output m_axis_phase_tvalid;
|
||||
output [31:0]m_axis_phase_tdata;
|
||||
output event_s_config_tlast_missing;
|
||||
output event_s_config_tlast_unexpected;
|
||||
endmodule
|
||||
@@ -0,0 +1,42 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
|
||||
-- Date : Thu Aug 17 17:22:27 2023
|
||||
-- Host : wlbpc running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_stub.vhdl
|
||||
-- Design : dds_stim_16ch
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_stim_16ch is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aclken : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
s_axis_config_tlast : in STD_LOGIC;
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_phase_tvalid : out STD_LOGIC;
|
||||
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
event_s_config_tlast_missing : out STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : out STD_LOGIC
|
||||
);
|
||||
|
||||
end dds_stim_16ch;
|
||||
|
||||
architecture stub of dds_stim_16ch is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aclken,aresetn,s_axis_config_tvalid,s_axis_config_tdata[63:0],s_axis_config_tlast,m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0],event_s_config_tlast_missing,event_s_config_tlast_unexpected";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_22,Vivado 2023.1.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:mult_gen:12.0
|
||||
// IP Revision: 18
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
mult_gen_au8_bu9_p8 your_instance_name (
|
||||
.CLK(CLK), // input wire CLK
|
||||
.A(A), // input wire [7 : 0] A
|
||||
.B(B), // input wire [8 : 0] B
|
||||
.CE(CE), // input wire CE
|
||||
.P(P) // output wire [7 : 0] P
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file mult_gen_au8_bu9_p8.v when simulating
|
||||
// the core, mult_gen_au8_bu9_p8. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
|
||||
-- IP Revision: 18
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT mult_gen_au8_bu9_p8
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
CE : IN STD_LOGIC;
|
||||
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : mult_gen_au8_bu9_p8
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
A => A,
|
||||
B => B,
|
||||
CE => CE,
|
||||
P => P
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file mult_gen_au8_bu9_p8.vhd when simulating
|
||||
-- the core, mult_gen_au8_bu9_p8. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
|
||||
|
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Reference in New Issue
Block a user