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chenmin
2024-10-28 13:14:49 +08:00
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
// Date : Wed Aug 16 19:04:11 2023
// Host : wlbpc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_xbar_0_stub.v
// Design : design_a9_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_29_axi_crossbar,Vivado 2023.1.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[143:0],m_axi_awaddr[383:0],m_axi_awlen[95:0],m_axi_awsize[35:0],m_axi_awburst[23:0],m_axi_awlock[11:0],m_axi_awcache[47:0],m_axi_awprot[35:0],m_axi_awregion[47:0],m_axi_awqos[47:0],m_axi_awvalid[11:0],m_axi_awready[11:0],m_axi_wdata[383:0],m_axi_wstrb[47:0],m_axi_wlast[11:0],m_axi_wvalid[11:0],m_axi_wready[11:0],m_axi_bid[143:0],m_axi_bresp[23:0],m_axi_bvalid[11:0],m_axi_bready[11:0],m_axi_arid[143:0],m_axi_araddr[383:0],m_axi_arlen[95:0],m_axi_arsize[35:0],m_axi_arburst[23:0],m_axi_arlock[11:0],m_axi_arcache[47:0],m_axi_arprot[35:0],m_axi_arregion[47:0],m_axi_arqos[47:0],m_axi_arvalid[11:0],m_axi_arready[11:0],m_axi_rid[143:0],m_axi_rdata[383:0],m_axi_rresp[23:0],m_axi_rlast[11:0],m_axi_rvalid[11:0],m_axi_rready[11:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [143:0]m_axi_awid;
output [383:0]m_axi_awaddr;
output [95:0]m_axi_awlen;
output [35:0]m_axi_awsize;
output [23:0]m_axi_awburst;
output [11:0]m_axi_awlock;
output [47:0]m_axi_awcache;
output [35:0]m_axi_awprot;
output [47:0]m_axi_awregion;
output [47:0]m_axi_awqos;
output [11:0]m_axi_awvalid;
input [11:0]m_axi_awready;
output [383:0]m_axi_wdata;
output [47:0]m_axi_wstrb;
output [11:0]m_axi_wlast;
output [11:0]m_axi_wvalid;
input [11:0]m_axi_wready;
input [143:0]m_axi_bid;
input [23:0]m_axi_bresp;
input [11:0]m_axi_bvalid;
output [11:0]m_axi_bready;
output [143:0]m_axi_arid;
output [383:0]m_axi_araddr;
output [95:0]m_axi_arlen;
output [35:0]m_axi_arsize;
output [23:0]m_axi_arburst;
output [11:0]m_axi_arlock;
output [47:0]m_axi_arcache;
output [35:0]m_axi_arprot;
output [47:0]m_axi_arregion;
output [47:0]m_axi_arqos;
output [11:0]m_axi_arvalid;
input [11:0]m_axi_arready;
input [143:0]m_axi_rid;
input [383:0]m_axi_rdata;
input [23:0]m_axi_rresp;
input [11:0]m_axi_rlast;
input [11:0]m_axi_rvalid;
output [11:0]m_axi_rready;
endmodule
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
-- Date : Wed Aug 16 19:04:11 2023
-- Host : wlbpc running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_xbar_0_stub.vhdl
-- Design : design_a9_1_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 143 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 383 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 383 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 143 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 143 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 383 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 143 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 383 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[143:0],m_axi_awaddr[383:0],m_axi_awlen[95:0],m_axi_awsize[35:0],m_axi_awburst[23:0],m_axi_awlock[11:0],m_axi_awcache[47:0],m_axi_awprot[35:0],m_axi_awregion[47:0],m_axi_awqos[47:0],m_axi_awvalid[11:0],m_axi_awready[11:0],m_axi_wdata[383:0],m_axi_wstrb[47:0],m_axi_wlast[11:0],m_axi_wvalid[11:0],m_axi_wready[11:0],m_axi_bid[143:0],m_axi_bresp[23:0],m_axi_bvalid[11:0],m_axi_bready[11:0],m_axi_arid[143:0],m_axi_araddr[383:0],m_axi_arlen[95:0],m_axi_arsize[35:0],m_axi_arburst[23:0],m_axi_arlock[11:0],m_axi_arcache[47:0],m_axi_arprot[35:0],m_axi_arregion[47:0],m_axi_arqos[47:0],m_axi_arvalid[11:0],m_axi_arready[11:0],m_axi_rid[143:0],m_axi_rdata[383:0],m_axi_rresp[23:0],m_axi_rlast[11:0],m_axi_rvalid[11:0],m_axi_rready[11:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_29_axi_crossbar,Vivado 2023.1.1";
begin
end;
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NumberHits:1
Timestamp: Thu Aug 17 06:05:40 UTC 2023