上传PL工程
This commit is contained in:
chenmin
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>9264329b52dca8fb</spirit:name>
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<spirit:componentInstance>
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<spirit:instanceName>design_a9_1_axi_fifo_mm_s_0_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_fifo_mm_s" spirit:version="4.3"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.FREQ_HZ">50000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.FREQ_HZ">50000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI4_BASEADDR">0x80001000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_RXD_PROTOCOL">XIL_AXI_STREAM_ETH_DATA</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_RXD_TDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXC_PROTOCOL">XIL_AXI_STREAM_ETH_CTRL</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXC_TDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_PROTOCOL">XIL_AXI_STREAM_ETH_DATA</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_TDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BASEADDR">0x43C00000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TSTRB">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TUSER">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x43C0FFFF</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_CASCADE_HEIGHT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_FIFO_DEPTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_CASCADE_HEIGHT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">480</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_CUT_THROUGH">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_CUT_THROUGH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_fifo_mm_s_0_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_ENABLE_ECC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">9264329b52dca8fb</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3895624 $</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">ec300c60</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">165</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
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// Date : Mon Jul 31 19:44:46 2023
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// Host : wlbpc running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_fifo_mm_s_0_0_stub.v
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// Design : design_a9_1_axi_fifo_mm_s_0_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z010clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_fifo_mm_s,Vivado 2023.1.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(interrupt, s_axi_aclk, s_axi_aresetn,
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s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready,
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mm2s_prmry_reset_out_n, axi_str_txd_tvalid, axi_str_txd_tready, axi_str_txd_tlast,
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axi_str_txd_tdata, s2mm_prmry_reset_out_n, axi_str_rxd_tvalid, axi_str_rxd_tready,
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axi_str_rxd_tlast, axi_str_rxd_tdata)
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/* synthesis syn_black_box black_box_pad_pin="interrupt,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,mm2s_prmry_reset_out_n,axi_str_txd_tvalid,axi_str_txd_tready,axi_str_txd_tlast,axi_str_txd_tdata[31:0],s2mm_prmry_reset_out_n,axi_str_rxd_tvalid,axi_str_rxd_tready,axi_str_rxd_tlast,axi_str_rxd_tdata[31:0]" */
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/* synthesis syn_force_seq_prim="s_axi_aclk" */;
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output interrupt;
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input s_axi_aclk /* synthesis syn_isclock = 1 */;
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input s_axi_aresetn;
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input [31:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [31:0]s_axi_araddr;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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output mm2s_prmry_reset_out_n;
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output axi_str_txd_tvalid;
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input axi_str_txd_tready;
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output axi_str_txd_tlast;
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output [31:0]axi_str_txd_tdata;
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output s2mm_prmry_reset_out_n;
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input axi_str_rxd_tvalid;
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output axi_str_rxd_tready;
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input axi_str_rxd_tlast;
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input [31:0]axi_str_rxd_tdata;
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endmodule
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+60
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2023.1.1 (win64) Build 3900603 Fri Jun 16 19:31:24 MDT 2023
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-- Date : Mon Jul 31 19:44:46 2023
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-- Host : wlbpc running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_fifo_mm_s_0_0_stub.vhdl
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-- Design : design_a9_1_axi_fifo_mm_s_0_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z010clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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interrupt : out STD_LOGIC;
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s_axi_aclk : in STD_LOGIC;
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s_axi_aresetn : in STD_LOGIC;
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s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_awvalid : in STD_LOGIC;
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s_axi_awready : out STD_LOGIC;
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s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
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s_axi_wvalid : in STD_LOGIC;
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s_axi_wready : out STD_LOGIC;
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s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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s_axi_bvalid : out STD_LOGIC;
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s_axi_bready : in STD_LOGIC;
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s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_arvalid : in STD_LOGIC;
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s_axi_arready : out STD_LOGIC;
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s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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s_axi_rvalid : out STD_LOGIC;
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s_axi_rready : in STD_LOGIC;
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mm2s_prmry_reset_out_n : out STD_LOGIC;
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axi_str_txd_tvalid : out STD_LOGIC;
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axi_str_txd_tready : in STD_LOGIC;
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axi_str_txd_tlast : out STD_LOGIC;
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axi_str_txd_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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s2mm_prmry_reset_out_n : out STD_LOGIC;
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axi_str_rxd_tvalid : in STD_LOGIC;
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axi_str_rxd_tready : out STD_LOGIC;
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axi_str_rxd_tlast : in STD_LOGIC;
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axi_str_rxd_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "interrupt,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,mm2s_prmry_reset_out_n,axi_str_txd_tvalid,axi_str_txd_tready,axi_str_txd_tlast,axi_str_txd_tdata[31:0],s2mm_prmry_reset_out_n,axi_str_rxd_tvalid,axi_str_rxd_tready,axi_str_rxd_tlast,axi_str_rxd_tdata[31:0]";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "axi_fifo_mm_s,Vivado 2023.1.1";
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begin
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end;
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