上传PL工程
This commit is contained in:
chenmin
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<?xml version="1.0" encoding="UTF-8"?>
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</spirit:configurableElementValues>
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</spirit:design>
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Binary file not shown.
File diff suppressed because one or more lines are too long
+107289
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,250 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 16 09:53:09 2023
|
||||
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_smc_0_stub.v
|
||||
// Design : design_a9_1_axi_smc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_6e35,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_awid, S00_AXI_awaddr,
|
||||
S00_AXI_awlen, S00_AXI_awsize, S00_AXI_awburst, S00_AXI_awlock, S00_AXI_awcache,
|
||||
S00_AXI_awprot, S00_AXI_awqos, S00_AXI_awvalid, S00_AXI_awready, S00_AXI_wid,
|
||||
S00_AXI_wdata, S00_AXI_wstrb, S00_AXI_wlast, S00_AXI_wvalid, S00_AXI_wready, S00_AXI_bid,
|
||||
S00_AXI_bresp, S00_AXI_bvalid, S00_AXI_bready, S00_AXI_arid, S00_AXI_araddr, S00_AXI_arlen,
|
||||
S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
|
||||
S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rid, S00_AXI_rdata, S00_AXI_rresp,
|
||||
S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, M00_AXI_awaddr, M00_AXI_awprot,
|
||||
M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wvalid,
|
||||
M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready, M00_AXI_araddr,
|
||||
M00_AXI_arprot, M00_AXI_arvalid, M00_AXI_arready, M00_AXI_rdata, M00_AXI_rresp,
|
||||
M00_AXI_rvalid, M00_AXI_rready, M01_AXI_awaddr, M01_AXI_awprot, M01_AXI_awvalid,
|
||||
M01_AXI_awready, M01_AXI_wdata, M01_AXI_wstrb, M01_AXI_wvalid, M01_AXI_wready,
|
||||
M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_bready, M01_AXI_araddr, M01_AXI_arprot,
|
||||
M01_AXI_arvalid, M01_AXI_arready, M01_AXI_rdata, M01_AXI_rresp, M01_AXI_rvalid,
|
||||
M01_AXI_rready, M02_AXI_awaddr, M02_AXI_awprot, M02_AXI_awvalid, M02_AXI_awready,
|
||||
M02_AXI_wdata, M02_AXI_wstrb, M02_AXI_wvalid, M02_AXI_wready, M02_AXI_bresp,
|
||||
M02_AXI_bvalid, M02_AXI_bready, M02_AXI_araddr, M02_AXI_arprot, M02_AXI_arvalid,
|
||||
M02_AXI_arready, M02_AXI_rdata, M02_AXI_rresp, M02_AXI_rvalid, M02_AXI_rready,
|
||||
M03_AXI_awaddr, M03_AXI_awprot, M03_AXI_awvalid, M03_AXI_awready, M03_AXI_wdata,
|
||||
M03_AXI_wstrb, M03_AXI_wvalid, M03_AXI_wready, M03_AXI_bresp, M03_AXI_bvalid,
|
||||
M03_AXI_bready, M03_AXI_araddr, M03_AXI_arprot, M03_AXI_arvalid, M03_AXI_arready,
|
||||
M03_AXI_rdata, M03_AXI_rresp, M03_AXI_rvalid, M03_AXI_rready, M04_AXI_awaddr,
|
||||
M04_AXI_awprot, M04_AXI_awvalid, M04_AXI_awready, M04_AXI_wdata, M04_AXI_wstrb,
|
||||
M04_AXI_wvalid, M04_AXI_wready, M04_AXI_bresp, M04_AXI_bvalid, M04_AXI_bready,
|
||||
M04_AXI_araddr, M04_AXI_arprot, M04_AXI_arvalid, M04_AXI_arready, M04_AXI_rdata,
|
||||
M04_AXI_rresp, M04_AXI_rvalid, M04_AXI_rready, M05_AXI_awaddr, M05_AXI_awprot,
|
||||
M05_AXI_awvalid, M05_AXI_awready, M05_AXI_wdata, M05_AXI_wstrb, M05_AXI_wvalid,
|
||||
M05_AXI_wready, M05_AXI_bresp, M05_AXI_bvalid, M05_AXI_bready, M05_AXI_araddr,
|
||||
M05_AXI_arprot, M05_AXI_arvalid, M05_AXI_arready, M05_AXI_rdata, M05_AXI_rresp,
|
||||
M05_AXI_rvalid, M05_AXI_rready, M06_AXI_awaddr, M06_AXI_awprot, M06_AXI_awvalid,
|
||||
M06_AXI_awready, M06_AXI_wdata, M06_AXI_wstrb, M06_AXI_wvalid, M06_AXI_wready,
|
||||
M06_AXI_bresp, M06_AXI_bvalid, M06_AXI_bready, M06_AXI_araddr, M06_AXI_arprot,
|
||||
M06_AXI_arvalid, M06_AXI_arready, M06_AXI_rdata, M06_AXI_rresp, M06_AXI_rvalid,
|
||||
M06_AXI_rready, M07_AXI_awaddr, M07_AXI_awprot, M07_AXI_awvalid, M07_AXI_awready,
|
||||
M07_AXI_wdata, M07_AXI_wstrb, M07_AXI_wvalid, M07_AXI_wready, M07_AXI_bresp,
|
||||
M07_AXI_bvalid, M07_AXI_bready, M07_AXI_araddr, M07_AXI_arprot, M07_AXI_arvalid,
|
||||
M07_AXI_arready, M07_AXI_rdata, M07_AXI_rresp, M07_AXI_rvalid, M07_AXI_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,S00_AXI_awid[11:0],S00_AXI_awaddr[31:0],S00_AXI_awlen[3:0],S00_AXI_awsize[2:0],S00_AXI_awburst[1:0],S00_AXI_awlock[1:0],S00_AXI_awcache[3:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awvalid,S00_AXI_awready,S00_AXI_wid[11:0],S00_AXI_wdata[31:0],S00_AXI_wstrb[3:0],S00_AXI_wlast,S00_AXI_wvalid,S00_AXI_wready,S00_AXI_bid[11:0],S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_bready,S00_AXI_arid[11:0],S00_AXI_araddr[31:0],S00_AXI_arlen[3:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[1:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rid[11:0],S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,M00_AXI_awaddr[12:0],M00_AXI_awprot[2:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[12:0],M00_AXI_arprot[2:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rvalid,M00_AXI_rready,M01_AXI_awaddr[8:0],M01_AXI_awprot[2:0],M01_AXI_awvalid,M01_AXI_awready,M01_AXI_wdata[31:0],M01_AXI_wstrb[3:0],M01_AXI_wvalid,M01_AXI_wready,M01_AXI_bresp[1:0],M01_AXI_bvalid,M01_AXI_bready,M01_AXI_araddr[8:0],M01_AXI_arprot[2:0],M01_AXI_arvalid,M01_AXI_arready,M01_AXI_rdata[31:0],M01_AXI_rresp[1:0],M01_AXI_rvalid,M01_AXI_rready,M02_AXI_awaddr[12:0],M02_AXI_awprot[2:0],M02_AXI_awvalid,M02_AXI_awready,M02_AXI_wdata[31:0],M02_AXI_wstrb[3:0],M02_AXI_wvalid,M02_AXI_wready,M02_AXI_bresp[1:0],M02_AXI_bvalid,M02_AXI_bready,M02_AXI_araddr[12:0],M02_AXI_arprot[2:0],M02_AXI_arvalid,M02_AXI_arready,M02_AXI_rdata[31:0],M02_AXI_rresp[1:0],M02_AXI_rvalid,M02_AXI_rready,M03_AXI_awaddr[12:0],M03_AXI_awprot[2:0],M03_AXI_awvalid,M03_AXI_awready,M03_AXI_wdata[31:0],M03_AXI_wstrb[3:0],M03_AXI_wvalid,M03_AXI_wready,M03_AXI_bresp[1:0],M03_AXI_bvalid,M03_AXI_bready,M03_AXI_araddr[12:0],M03_AXI_arprot[2:0],M03_AXI_arvalid,M03_AXI_arready,M03_AXI_rdata[31:0],M03_AXI_rresp[1:0],M03_AXI_rvalid,M03_AXI_rready,M04_AXI_awaddr[8:0],M04_AXI_awprot[2:0],M04_AXI_awvalid,M04_AXI_awready,M04_AXI_wdata[31:0],M04_AXI_wstrb[3:0],M04_AXI_wvalid,M04_AXI_wready,M04_AXI_bresp[1:0],M04_AXI_bvalid,M04_AXI_bready,M04_AXI_araddr[8:0],M04_AXI_arprot[2:0],M04_AXI_arvalid,M04_AXI_arready,M04_AXI_rdata[31:0],M04_AXI_rresp[1:0],M04_AXI_rvalid,M04_AXI_rready,M05_AXI_awaddr[6:0],M05_AXI_awprot[2:0],M05_AXI_awvalid,M05_AXI_awready,M05_AXI_wdata[31:0],M05_AXI_wstrb[3:0],M05_AXI_wvalid,M05_AXI_wready,M05_AXI_bresp[1:0],M05_AXI_bvalid,M05_AXI_bready,M05_AXI_araddr[6:0],M05_AXI_arprot[2:0],M05_AXI_arvalid,M05_AXI_arready,M05_AXI_rdata[31:0],M05_AXI_rresp[1:0],M05_AXI_rvalid,M05_AXI_rready,M06_AXI_awaddr[31:0],M06_AXI_awprot[2:0],M06_AXI_awvalid,M06_AXI_awready,M06_AXI_wdata[31:0],M06_AXI_wstrb[3:0],M06_AXI_wvalid,M06_AXI_wready,M06_AXI_bresp[1:0],M06_AXI_bvalid,M06_AXI_bready,M06_AXI_araddr[31:0],M06_AXI_arprot[2:0],M06_AXI_arvalid,M06_AXI_arready,M06_AXI_rdata[31:0],M06_AXI_rresp[1:0],M06_AXI_rvalid,M06_AXI_rready,M07_AXI_awaddr[9:0],M07_AXI_awprot[2:0],M07_AXI_awvalid,M07_AXI_awready,M07_AXI_wdata[31:0],M07_AXI_wstrb[3:0],M07_AXI_wvalid,M07_AXI_wready,M07_AXI_bresp[1:0],M07_AXI_bvalid,M07_AXI_bready,M07_AXI_araddr[9:0],M07_AXI_arprot[2:0],M07_AXI_arvalid,M07_AXI_arready,M07_AXI_rdata[31:0],M07_AXI_rresp[1:0],M07_AXI_rvalid,M07_AXI_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [11:0]S00_AXI_awid;
|
||||
input [31:0]S00_AXI_awaddr;
|
||||
input [3:0]S00_AXI_awlen;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [1:0]S00_AXI_awlock;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
input S00_AXI_awvalid;
|
||||
output S00_AXI_awready;
|
||||
input [11:0]S00_AXI_wid;
|
||||
input [31:0]S00_AXI_wdata;
|
||||
input [3:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wlast;
|
||||
input S00_AXI_wvalid;
|
||||
output S00_AXI_wready;
|
||||
output [11:0]S00_AXI_bid;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
input S00_AXI_bready;
|
||||
input [11:0]S00_AXI_arid;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [3:0]S00_AXI_arlen;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [1:0]S00_AXI_arlock;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
input S00_AXI_arvalid;
|
||||
output S00_AXI_arready;
|
||||
output [11:0]S00_AXI_rid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rlast;
|
||||
output S00_AXI_rvalid;
|
||||
input S00_AXI_rready;
|
||||
output [12:0]M00_AXI_awaddr;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output M00_AXI_awvalid;
|
||||
input M00_AXI_awready;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input M00_AXI_wready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
output M00_AXI_bready;
|
||||
output [12:0]M00_AXI_araddr;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output M00_AXI_arvalid;
|
||||
input M00_AXI_arready;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output M00_AXI_rready;
|
||||
output [8:0]M01_AXI_awaddr;
|
||||
output [2:0]M01_AXI_awprot;
|
||||
output M01_AXI_awvalid;
|
||||
input M01_AXI_awready;
|
||||
output [31:0]M01_AXI_wdata;
|
||||
output [3:0]M01_AXI_wstrb;
|
||||
output M01_AXI_wvalid;
|
||||
input M01_AXI_wready;
|
||||
input [1:0]M01_AXI_bresp;
|
||||
input M01_AXI_bvalid;
|
||||
output M01_AXI_bready;
|
||||
output [8:0]M01_AXI_araddr;
|
||||
output [2:0]M01_AXI_arprot;
|
||||
output M01_AXI_arvalid;
|
||||
input M01_AXI_arready;
|
||||
input [31:0]M01_AXI_rdata;
|
||||
input [1:0]M01_AXI_rresp;
|
||||
input M01_AXI_rvalid;
|
||||
output M01_AXI_rready;
|
||||
output [12:0]M02_AXI_awaddr;
|
||||
output [2:0]M02_AXI_awprot;
|
||||
output M02_AXI_awvalid;
|
||||
input M02_AXI_awready;
|
||||
output [31:0]M02_AXI_wdata;
|
||||
output [3:0]M02_AXI_wstrb;
|
||||
output M02_AXI_wvalid;
|
||||
input M02_AXI_wready;
|
||||
input [1:0]M02_AXI_bresp;
|
||||
input M02_AXI_bvalid;
|
||||
output M02_AXI_bready;
|
||||
output [12:0]M02_AXI_araddr;
|
||||
output [2:0]M02_AXI_arprot;
|
||||
output M02_AXI_arvalid;
|
||||
input M02_AXI_arready;
|
||||
input [31:0]M02_AXI_rdata;
|
||||
input [1:0]M02_AXI_rresp;
|
||||
input M02_AXI_rvalid;
|
||||
output M02_AXI_rready;
|
||||
output [12:0]M03_AXI_awaddr;
|
||||
output [2:0]M03_AXI_awprot;
|
||||
output M03_AXI_awvalid;
|
||||
input M03_AXI_awready;
|
||||
output [31:0]M03_AXI_wdata;
|
||||
output [3:0]M03_AXI_wstrb;
|
||||
output M03_AXI_wvalid;
|
||||
input M03_AXI_wready;
|
||||
input [1:0]M03_AXI_bresp;
|
||||
input M03_AXI_bvalid;
|
||||
output M03_AXI_bready;
|
||||
output [12:0]M03_AXI_araddr;
|
||||
output [2:0]M03_AXI_arprot;
|
||||
output M03_AXI_arvalid;
|
||||
input M03_AXI_arready;
|
||||
input [31:0]M03_AXI_rdata;
|
||||
input [1:0]M03_AXI_rresp;
|
||||
input M03_AXI_rvalid;
|
||||
output M03_AXI_rready;
|
||||
output [8:0]M04_AXI_awaddr;
|
||||
output [2:0]M04_AXI_awprot;
|
||||
output M04_AXI_awvalid;
|
||||
input M04_AXI_awready;
|
||||
output [31:0]M04_AXI_wdata;
|
||||
output [3:0]M04_AXI_wstrb;
|
||||
output M04_AXI_wvalid;
|
||||
input M04_AXI_wready;
|
||||
input [1:0]M04_AXI_bresp;
|
||||
input M04_AXI_bvalid;
|
||||
output M04_AXI_bready;
|
||||
output [8:0]M04_AXI_araddr;
|
||||
output [2:0]M04_AXI_arprot;
|
||||
output M04_AXI_arvalid;
|
||||
input M04_AXI_arready;
|
||||
input [31:0]M04_AXI_rdata;
|
||||
input [1:0]M04_AXI_rresp;
|
||||
input M04_AXI_rvalid;
|
||||
output M04_AXI_rready;
|
||||
output [6:0]M05_AXI_awaddr;
|
||||
output [2:0]M05_AXI_awprot;
|
||||
output M05_AXI_awvalid;
|
||||
input M05_AXI_awready;
|
||||
output [31:0]M05_AXI_wdata;
|
||||
output [3:0]M05_AXI_wstrb;
|
||||
output M05_AXI_wvalid;
|
||||
input M05_AXI_wready;
|
||||
input [1:0]M05_AXI_bresp;
|
||||
input M05_AXI_bvalid;
|
||||
output M05_AXI_bready;
|
||||
output [6:0]M05_AXI_araddr;
|
||||
output [2:0]M05_AXI_arprot;
|
||||
output M05_AXI_arvalid;
|
||||
input M05_AXI_arready;
|
||||
input [31:0]M05_AXI_rdata;
|
||||
input [1:0]M05_AXI_rresp;
|
||||
input M05_AXI_rvalid;
|
||||
output M05_AXI_rready;
|
||||
output [31:0]M06_AXI_awaddr;
|
||||
output [2:0]M06_AXI_awprot;
|
||||
output M06_AXI_awvalid;
|
||||
input M06_AXI_awready;
|
||||
output [31:0]M06_AXI_wdata;
|
||||
output [3:0]M06_AXI_wstrb;
|
||||
output M06_AXI_wvalid;
|
||||
input M06_AXI_wready;
|
||||
input [1:0]M06_AXI_bresp;
|
||||
input M06_AXI_bvalid;
|
||||
output M06_AXI_bready;
|
||||
output [31:0]M06_AXI_araddr;
|
||||
output [2:0]M06_AXI_arprot;
|
||||
output M06_AXI_arvalid;
|
||||
input M06_AXI_arready;
|
||||
input [31:0]M06_AXI_rdata;
|
||||
input [1:0]M06_AXI_rresp;
|
||||
input M06_AXI_rvalid;
|
||||
output M06_AXI_rready;
|
||||
output [9:0]M07_AXI_awaddr;
|
||||
output [2:0]M07_AXI_awprot;
|
||||
output M07_AXI_awvalid;
|
||||
input M07_AXI_awready;
|
||||
output [31:0]M07_AXI_wdata;
|
||||
output [3:0]M07_AXI_wstrb;
|
||||
output M07_AXI_wvalid;
|
||||
input M07_AXI_wready;
|
||||
input [1:0]M07_AXI_bresp;
|
||||
input M07_AXI_bvalid;
|
||||
output M07_AXI_bready;
|
||||
output [9:0]M07_AXI_araddr;
|
||||
output [2:0]M07_AXI_arprot;
|
||||
output M07_AXI_arvalid;
|
||||
input M07_AXI_arready;
|
||||
input [31:0]M07_AXI_rdata;
|
||||
input [1:0]M07_AXI_rresp;
|
||||
input M07_AXI_rvalid;
|
||||
output M07_AXI_rready;
|
||||
endmodule
|
||||
@@ -0,0 +1,222 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 16 09:53:09 2023
|
||||
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_smc_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_smc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awvalid : in STD_LOGIC;
|
||||
S00_AXI_awready : out STD_LOGIC;
|
||||
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_wlast : in STD_LOGIC;
|
||||
S00_AXI_wvalid : in STD_LOGIC;
|
||||
S00_AXI_wready : out STD_LOGIC;
|
||||
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_bvalid : out STD_LOGIC;
|
||||
S00_AXI_bready : in STD_LOGIC;
|
||||
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arvalid : in STD_LOGIC;
|
||||
S00_AXI_arready : out STD_LOGIC;
|
||||
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_rlast : out STD_LOGIC;
|
||||
S00_AXI_rvalid : out STD_LOGIC;
|
||||
S00_AXI_rready : in STD_LOGIC;
|
||||
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awvalid : out STD_LOGIC;
|
||||
M00_AXI_awready : in STD_LOGIC;
|
||||
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_wvalid : out STD_LOGIC;
|
||||
M00_AXI_wready : in STD_LOGIC;
|
||||
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_bvalid : in STD_LOGIC;
|
||||
M00_AXI_bready : out STD_LOGIC;
|
||||
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arvalid : out STD_LOGIC;
|
||||
M00_AXI_arready : in STD_LOGIC;
|
||||
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_rvalid : in STD_LOGIC;
|
||||
M00_AXI_rready : out STD_LOGIC;
|
||||
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M01_AXI_awvalid : out STD_LOGIC;
|
||||
M01_AXI_awready : in STD_LOGIC;
|
||||
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M01_AXI_wvalid : out STD_LOGIC;
|
||||
M01_AXI_wready : in STD_LOGIC;
|
||||
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M01_AXI_bvalid : in STD_LOGIC;
|
||||
M01_AXI_bready : out STD_LOGIC;
|
||||
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M01_AXI_arvalid : out STD_LOGIC;
|
||||
M01_AXI_arready : in STD_LOGIC;
|
||||
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M01_AXI_rvalid : in STD_LOGIC;
|
||||
M01_AXI_rready : out STD_LOGIC;
|
||||
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M02_AXI_awvalid : out STD_LOGIC;
|
||||
M02_AXI_awready : in STD_LOGIC;
|
||||
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M02_AXI_wvalid : out STD_LOGIC;
|
||||
M02_AXI_wready : in STD_LOGIC;
|
||||
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M02_AXI_bvalid : in STD_LOGIC;
|
||||
M02_AXI_bready : out STD_LOGIC;
|
||||
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M02_AXI_arvalid : out STD_LOGIC;
|
||||
M02_AXI_arready : in STD_LOGIC;
|
||||
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M02_AXI_rvalid : in STD_LOGIC;
|
||||
M02_AXI_rready : out STD_LOGIC;
|
||||
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M03_AXI_awvalid : out STD_LOGIC;
|
||||
M03_AXI_awready : in STD_LOGIC;
|
||||
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M03_AXI_wvalid : out STD_LOGIC;
|
||||
M03_AXI_wready : in STD_LOGIC;
|
||||
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M03_AXI_bvalid : in STD_LOGIC;
|
||||
M03_AXI_bready : out STD_LOGIC;
|
||||
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M03_AXI_arvalid : out STD_LOGIC;
|
||||
M03_AXI_arready : in STD_LOGIC;
|
||||
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M03_AXI_rvalid : in STD_LOGIC;
|
||||
M03_AXI_rready : out STD_LOGIC;
|
||||
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
M04_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M04_AXI_awvalid : out STD_LOGIC;
|
||||
M04_AXI_awready : in STD_LOGIC;
|
||||
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M04_AXI_wvalid : out STD_LOGIC;
|
||||
M04_AXI_wready : in STD_LOGIC;
|
||||
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M04_AXI_bvalid : in STD_LOGIC;
|
||||
M04_AXI_bready : out STD_LOGIC;
|
||||
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
M04_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M04_AXI_arvalid : out STD_LOGIC;
|
||||
M04_AXI_arready : in STD_LOGIC;
|
||||
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M04_AXI_rvalid : in STD_LOGIC;
|
||||
M04_AXI_rready : out STD_LOGIC;
|
||||
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
M05_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M05_AXI_awvalid : out STD_LOGIC;
|
||||
M05_AXI_awready : in STD_LOGIC;
|
||||
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M05_AXI_wvalid : out STD_LOGIC;
|
||||
M05_AXI_wready : in STD_LOGIC;
|
||||
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M05_AXI_bvalid : in STD_LOGIC;
|
||||
M05_AXI_bready : out STD_LOGIC;
|
||||
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
M05_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M05_AXI_arvalid : out STD_LOGIC;
|
||||
M05_AXI_arready : in STD_LOGIC;
|
||||
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M05_AXI_rvalid : in STD_LOGIC;
|
||||
M05_AXI_rready : out STD_LOGIC;
|
||||
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M06_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M06_AXI_awvalid : out STD_LOGIC;
|
||||
M06_AXI_awready : in STD_LOGIC;
|
||||
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M06_AXI_wvalid : out STD_LOGIC;
|
||||
M06_AXI_wready : in STD_LOGIC;
|
||||
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M06_AXI_bvalid : in STD_LOGIC;
|
||||
M06_AXI_bready : out STD_LOGIC;
|
||||
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M06_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M06_AXI_arvalid : out STD_LOGIC;
|
||||
M06_AXI_arready : in STD_LOGIC;
|
||||
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M06_AXI_rvalid : in STD_LOGIC;
|
||||
M06_AXI_rready : out STD_LOGIC;
|
||||
M07_AXI_awaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
M07_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M07_AXI_awvalid : out STD_LOGIC;
|
||||
M07_AXI_awready : in STD_LOGIC;
|
||||
M07_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M07_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M07_AXI_wvalid : out STD_LOGIC;
|
||||
M07_AXI_wready : in STD_LOGIC;
|
||||
M07_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M07_AXI_bvalid : in STD_LOGIC;
|
||||
M07_AXI_bready : out STD_LOGIC;
|
||||
M07_AXI_araddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
M07_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M07_AXI_arvalid : out STD_LOGIC;
|
||||
M07_AXI_arready : in STD_LOGIC;
|
||||
M07_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M07_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M07_AXI_rvalid : in STD_LOGIC;
|
||||
M07_AXI_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_awid[11:0],S00_AXI_awaddr[31:0],S00_AXI_awlen[3:0],S00_AXI_awsize[2:0],S00_AXI_awburst[1:0],S00_AXI_awlock[1:0],S00_AXI_awcache[3:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awvalid,S00_AXI_awready,S00_AXI_wid[11:0],S00_AXI_wdata[31:0],S00_AXI_wstrb[3:0],S00_AXI_wlast,S00_AXI_wvalid,S00_AXI_wready,S00_AXI_bid[11:0],S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_bready,S00_AXI_arid[11:0],S00_AXI_araddr[31:0],S00_AXI_arlen[3:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[1:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rid[11:0],S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,M00_AXI_awaddr[12:0],M00_AXI_awprot[2:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[12:0],M00_AXI_arprot[2:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rvalid,M00_AXI_rready,M01_AXI_awaddr[8:0],M01_AXI_awprot[2:0],M01_AXI_awvalid,M01_AXI_awready,M01_AXI_wdata[31:0],M01_AXI_wstrb[3:0],M01_AXI_wvalid,M01_AXI_wready,M01_AXI_bresp[1:0],M01_AXI_bvalid,M01_AXI_bready,M01_AXI_araddr[8:0],M01_AXI_arprot[2:0],M01_AXI_arvalid,M01_AXI_arready,M01_AXI_rdata[31:0],M01_AXI_rresp[1:0],M01_AXI_rvalid,M01_AXI_rready,M02_AXI_awaddr[12:0],M02_AXI_awprot[2:0],M02_AXI_awvalid,M02_AXI_awready,M02_AXI_wdata[31:0],M02_AXI_wstrb[3:0],M02_AXI_wvalid,M02_AXI_wready,M02_AXI_bresp[1:0],M02_AXI_bvalid,M02_AXI_bready,M02_AXI_araddr[12:0],M02_AXI_arprot[2:0],M02_AXI_arvalid,M02_AXI_arready,M02_AXI_rdata[31:0],M02_AXI_rresp[1:0],M02_AXI_rvalid,M02_AXI_rready,M03_AXI_awaddr[12:0],M03_AXI_awprot[2:0],M03_AXI_awvalid,M03_AXI_awready,M03_AXI_wdata[31:0],M03_AXI_wstrb[3:0],M03_AXI_wvalid,M03_AXI_wready,M03_AXI_bresp[1:0],M03_AXI_bvalid,M03_AXI_bready,M03_AXI_araddr[12:0],M03_AXI_arprot[2:0],M03_AXI_arvalid,M03_AXI_arready,M03_AXI_rdata[31:0],M03_AXI_rresp[1:0],M03_AXI_rvalid,M03_AXI_rready,M04_AXI_awaddr[8:0],M04_AXI_awprot[2:0],M04_AXI_awvalid,M04_AXI_awready,M04_AXI_wdata[31:0],M04_AXI_wstrb[3:0],M04_AXI_wvalid,M04_AXI_wready,M04_AXI_bresp[1:0],M04_AXI_bvalid,M04_AXI_bready,M04_AXI_araddr[8:0],M04_AXI_arprot[2:0],M04_AXI_arvalid,M04_AXI_arready,M04_AXI_rdata[31:0],M04_AXI_rresp[1:0],M04_AXI_rvalid,M04_AXI_rready,M05_AXI_awaddr[6:0],M05_AXI_awprot[2:0],M05_AXI_awvalid,M05_AXI_awready,M05_AXI_wdata[31:0],M05_AXI_wstrb[3:0],M05_AXI_wvalid,M05_AXI_wready,M05_AXI_bresp[1:0],M05_AXI_bvalid,M05_AXI_bready,M05_AXI_araddr[6:0],M05_AXI_arprot[2:0],M05_AXI_arvalid,M05_AXI_arready,M05_AXI_rdata[31:0],M05_AXI_rresp[1:0],M05_AXI_rvalid,M05_AXI_rready,M06_AXI_awaddr[31:0],M06_AXI_awprot[2:0],M06_AXI_awvalid,M06_AXI_awready,M06_AXI_wdata[31:0],M06_AXI_wstrb[3:0],M06_AXI_wvalid,M06_AXI_wready,M06_AXI_bresp[1:0],M06_AXI_bvalid,M06_AXI_bready,M06_AXI_araddr[31:0],M06_AXI_arprot[2:0],M06_AXI_arvalid,M06_AXI_arready,M06_AXI_rdata[31:0],M06_AXI_rresp[1:0],M06_AXI_rvalid,M06_AXI_rready,M07_AXI_awaddr[9:0],M07_AXI_awprot[2:0],M07_AXI_awvalid,M07_AXI_awready,M07_AXI_wdata[31:0],M07_AXI_wstrb[3:0],M07_AXI_wvalid,M07_AXI_wready,M07_AXI_bresp[1:0],M07_AXI_bvalid,M07_AXI_bready,M07_AXI_araddr[9:0],M07_AXI_arprot[2:0],M07_AXI_arvalid,M07_AXI_arready,M07_AXI_rdata[31:0],M07_AXI_rresp[1:0],M07_AXI_rvalid,M07_AXI_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_6e35,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Tue Oct 17 10:00:37 UTC 2023
|
||||
Reference in New Issue
Block a user