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chenmin
2024-10-28 13:14:49 +08:00
parent d9ea3b1c85
commit 25cdd3c44c
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c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/b9351c8a4eb9d8d3.xci
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c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/design_a9_1_axis_data_fifo_1_0.dcp
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c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/design_a9_1_axis_data_fifo_1_0_sim_netlist.v
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c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/design_a9_1_axis_data_fifo_1_0_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/design_a9_1_axis_data_fifo_1_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Jan 8 10:51:14 2024
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_1_0_stub.v
// Design : design_a9_1_axis_data_fifo_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
s_axis_tready, s_axis_tdata, s_axis_tlast, m_axis_tvalid, m_axis_tready, m_axis_tdata,
m_axis_tlast, prog_full)
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast,prog_full" */
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
input s_axis_aresetn;
input s_axis_aclk /* synthesis syn_isclock = 1 */;
input s_axis_tvalid;
output s_axis_tready;
input [31:0]s_axis_tdata;
input s_axis_tlast;
output m_axis_tvalid;
input m_axis_tready;
output [31:0]m_axis_tdata;
output m_axis_tlast;
output prog_full;
endmodule
c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/design_a9_1_axis_data_fifo_1_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Mon Jan 8 10:51:14 2024
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_1_0_stub.vhdl
-- Design : design_a9_1_axis_data_fifo_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tlast : out STD_LOGIC;
prog_full : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast,prog_full";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/b/9/b9351c8a4eb9d8d3/stats.txt
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Timestamp: Thu Mar 07 06:56:17 UTC 2024