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chenmin
2024-10-28 13:14:49 +08:00
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c64_pro.cache/ip/2023.1/1/f/1f52b31882e8198b/1f52b31882e8198b.xci
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c64_pro.cache/ip/2023.1/1/f/1f52b31882e8198b/design_a9_1_axi_dma_0_0.dcp
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c64_pro.cache/ip/2023.1/1/f/1f52b31882e8198b/design_a9_1_axi_dma_0_0_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/1/f/1f52b31882e8198b/design_a9_1_axi_dma_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Sep 20 11:10:41 2023
// Host : 840-5CG14025H4 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.v
// Design : design_a9_1_axi_dma_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_dma,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_lite_aclk, m_axi_mm2s_aclk,
m_axi_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr,
s_axi_lite_wvalid, s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp,
s_axi_lite_bvalid, s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready,
s_axi_lite_araddr, s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata,
s_axi_lite_rresp, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize,
m_axi_mm2s_arburst, m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid,
m_axi_mm2s_arready, m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast,
m_axi_mm2s_rvalid, m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata,
m_axis_mm2s_tkeep, m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast,
m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, m_axi_s2mm_awburst,
m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, m_axi_s2mm_awready,
m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, m_axi_s2mm_wvalid,
m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, m_axi_s2mm_bready,
s2mm_prmry_reset_out_n, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tvalid,
s_axis_s2mm_tready, s_axis_s2mm_tlast, mm2s_introut, s2mm_introut, axi_dma_tstvec)
/* synthesis syn_black_box black_box_pad_pin="axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]" */
/* synthesis syn_force_seq_prim="s_axi_lite_aclk" */
/* synthesis syn_force_seq_prim="m_axi_mm2s_aclk" */
/* synthesis syn_force_seq_prim="m_axi_s2mm_aclk" */;
input s_axi_lite_aclk /* synthesis syn_isclock = 1 */;
input m_axi_mm2s_aclk /* synthesis syn_isclock = 1 */;
input m_axi_s2mm_aclk /* synthesis syn_isclock = 1 */;
input axi_resetn;
input s_axi_lite_awvalid;
output s_axi_lite_awready;
input [9:0]s_axi_lite_awaddr;
input s_axi_lite_wvalid;
output s_axi_lite_wready;
input [31:0]s_axi_lite_wdata;
output [1:0]s_axi_lite_bresp;
output s_axi_lite_bvalid;
input s_axi_lite_bready;
input s_axi_lite_arvalid;
output s_axi_lite_arready;
input [9:0]s_axi_lite_araddr;
output s_axi_lite_rvalid;
input s_axi_lite_rready;
output [31:0]s_axi_lite_rdata;
output [1:0]s_axi_lite_rresp;
output [31:0]m_axi_mm2s_araddr;
output [7:0]m_axi_mm2s_arlen;
output [2:0]m_axi_mm2s_arsize;
output [1:0]m_axi_mm2s_arburst;
output [2:0]m_axi_mm2s_arprot;
output [3:0]m_axi_mm2s_arcache;
output m_axi_mm2s_arvalid;
input m_axi_mm2s_arready;
input [31:0]m_axi_mm2s_rdata;
input [1:0]m_axi_mm2s_rresp;
input m_axi_mm2s_rlast;
input m_axi_mm2s_rvalid;
output m_axi_mm2s_rready;
output mm2s_prmry_reset_out_n;
output [31:0]m_axis_mm2s_tdata;
output [3:0]m_axis_mm2s_tkeep;
output m_axis_mm2s_tvalid;
input m_axis_mm2s_tready;
output m_axis_mm2s_tlast;
output [31:0]m_axi_s2mm_awaddr;
output [7:0]m_axi_s2mm_awlen;
output [2:0]m_axi_s2mm_awsize;
output [1:0]m_axi_s2mm_awburst;
output [2:0]m_axi_s2mm_awprot;
output [3:0]m_axi_s2mm_awcache;
output m_axi_s2mm_awvalid;
input m_axi_s2mm_awready;
output [31:0]m_axi_s2mm_wdata;
output [3:0]m_axi_s2mm_wstrb;
output m_axi_s2mm_wlast;
output m_axi_s2mm_wvalid;
input m_axi_s2mm_wready;
input [1:0]m_axi_s2mm_bresp;
input m_axi_s2mm_bvalid;
output m_axi_s2mm_bready;
output s2mm_prmry_reset_out_n;
input [31:0]s_axis_s2mm_tdata;
input [3:0]s_axis_s2mm_tkeep;
input s_axis_s2mm_tvalid;
output s_axis_s2mm_tready;
input s_axis_s2mm_tlast;
output mm2s_introut;
output s2mm_introut;
output [31:0]axi_dma_tstvec;
endmodule
c64_pro.cache/ip/2023.1/1/f/1f52b31882e8198b/design_a9_1_axi_dma_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Sep 20 11:10:41 2023
-- Host : 840-5CG14025H4 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.vhdl
-- Design : design_a9_1_axi_dma_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC;
axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_dma,Vivado 2023.1";
begin
end;
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Timestamp: Wed Sep 20 03:23:25 UTC 2023