sync chunk 2/12
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@@ -0,0 +1,714 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Jun 24 13:53:32 2026
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// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ c_add_s16_s32_sim_netlist.v
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// Design : c_add_s16_s32
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// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
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// or synthesized. This netlist cannot be used for SDF annotated simulation.
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// Device : xc7z020clg400-2
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* CHECK_LICENSE_TYPE = "c_add_s16_s32,c_addsub_v12_0_15,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "c_addsub_v12_0_15,Vivado 2023.1" *)
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(* NotValidForBitStream *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
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(A,
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B,
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CLK,
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CE,
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SCLR,
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S);
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(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef" *) input [15:0]A;
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(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef" *) input [31:0]B;
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(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input CLK;
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(* x_interface_info = "xilinx.com:signal:clockenable:1.0 ce_intf CE" *) (* x_interface_parameter = "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_HIGH" *) input CE;
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(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) (* x_interface_parameter = "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input SCLR;
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(* x_interface_info = "xilinx.com:signal:data:1.0 s_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef" *) output [31:0]S;
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wire [15:0]A;
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wire [31:0]B;
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wire CE;
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wire CLK;
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wire [31:0]S;
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wire SCLR;
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wire NLW_U0_C_OUT_UNCONNECTED;
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(* C_AINIT_VAL = "0" *)
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(* C_BORROW_LOW = "1" *)
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||||
(* C_CE_OVERRIDES_BYPASS = "1" *)
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||||
(* C_CE_OVERRIDES_SCLR = "0" *)
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||||
(* C_HAS_CE = "1" *)
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(* C_HAS_SCLR = "1" *)
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(* C_HAS_SINIT = "0" *)
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||||
(* C_HAS_SSET = "0" *)
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(* C_IMPLEMENTATION = "0" *)
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(* C_SCLR_OVERRIDES_SSET = "1" *)
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(* C_SINIT_VAL = "0" *)
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||||
(* C_VERBOSITY = "0" *)
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(* C_XDEVICEFAMILY = "zynq" *)
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(* c_a_type = "0" *)
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(* c_a_width = "16" *)
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(* c_add_mode = "0" *)
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(* c_b_constant = "0" *)
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(* c_b_type = "0" *)
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(* c_b_value = "00000000000000000000000000000000" *)
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||||
(* c_b_width = "32" *)
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||||
(* c_bypass_low = "0" *)
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(* c_has_bypass = "0" *)
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(* c_has_c_in = "0" *)
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||||
(* c_has_c_out = "0" *)
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(* c_latency = "1" *)
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||||
(* c_out_width = "32" *)
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||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
(* is_du_within_envelope = "true" *)
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decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_c_addsub_v12_0_15 U0
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(.A(A),
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.ADD(1'b1),
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.B(B),
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.BYPASS(1'b0),
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.CE(CE),
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.CLK(CLK),
|
||||
.C_IN(1'b0),
|
||||
.C_OUT(NLW_U0_C_OUT_UNCONNECTED),
|
||||
.S(S),
|
||||
.SCLR(SCLR),
|
||||
.SINIT(1'b0),
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||||
.SSET(1'b0));
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||||
endmodule
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
|
||||
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25312)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
IzmD1g==
|
||||
`pragma protect end_protected
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,986 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:33 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ c_add_s16_s32_sim_netlist.vhdl
|
||||
-- Design : c_add_s16_s32
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
|
||||
`protect key_block
|
||||
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|
||||
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|
||||
d9c32tn+nnKzzv9Th4w=
|
||||
|
||||
`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`protect key_block
|
||||
HSlmGz2SGCvobOPHMYenk7mU0c+DtBwa7Ax0qqDDZTCg2rpnfjFWk5KT5JPGzDTKCKw1wIEr8Q/h
|
||||
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|
||||
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|
||||
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|
||||
bUAEamXp0byrWsvHHiXhXW805SN7ZUCheQZ3kQ==
|
||||
|
||||
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
|
||||
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
|
||||
`protect key_block
|
||||
T11EP6KjpQofUHaa2RkUYv1vV/ZNuOziYmezj3esxBsdErBwGPkunhOx4bQO1npLvky5TdRMdO8v
|
||||
ulO8okfTefde1iwvUNB+700NNvo47Lw1eUFprUO7Qjy1FUSyEwUhgv+ki4AEq8jFLPgeDvwOCERg
|
||||
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||||
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|
||||
`protect end_protected
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
CLK : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
SCLR : in STD_LOGIC;
|
||||
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "c_add_s16_s32,c_addsub_v12_0_15,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "c_addsub_v12_0_15,Vivado 2023.1";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
|
||||
attribute C_AINIT_VAL : string;
|
||||
attribute C_AINIT_VAL of U0 : label is "0";
|
||||
attribute C_BORROW_LOW : integer;
|
||||
attribute C_BORROW_LOW of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_BYPASS : integer;
|
||||
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_SCLR : integer;
|
||||
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
|
||||
attribute C_HAS_CE : integer;
|
||||
attribute C_HAS_CE of U0 : label is 1;
|
||||
attribute C_HAS_SCLR : integer;
|
||||
attribute C_HAS_SCLR of U0 : label is 1;
|
||||
attribute C_HAS_SINIT : integer;
|
||||
attribute C_HAS_SINIT of U0 : label is 0;
|
||||
attribute C_HAS_SSET : integer;
|
||||
attribute C_HAS_SSET of U0 : label is 0;
|
||||
attribute C_IMPLEMENTATION : integer;
|
||||
attribute C_IMPLEMENTATION of U0 : label is 0;
|
||||
attribute C_SCLR_OVERRIDES_SSET : integer;
|
||||
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
|
||||
attribute C_SINIT_VAL : string;
|
||||
attribute C_SINIT_VAL of U0 : label is "0";
|
||||
attribute C_VERBOSITY : integer;
|
||||
attribute C_VERBOSITY of U0 : label is 0;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
|
||||
attribute c_a_type : integer;
|
||||
attribute c_a_type of U0 : label is 0;
|
||||
attribute c_a_width : integer;
|
||||
attribute c_a_width of U0 : label is 16;
|
||||
attribute c_add_mode : integer;
|
||||
attribute c_add_mode of U0 : label is 0;
|
||||
attribute c_b_constant : integer;
|
||||
attribute c_b_constant of U0 : label is 0;
|
||||
attribute c_b_type : integer;
|
||||
attribute c_b_type of U0 : label is 0;
|
||||
attribute c_b_value : string;
|
||||
attribute c_b_value of U0 : label is "00000000000000000000000000000000";
|
||||
attribute c_b_width : integer;
|
||||
attribute c_b_width of U0 : label is 32;
|
||||
attribute c_bypass_low : integer;
|
||||
attribute c_bypass_low of U0 : label is 0;
|
||||
attribute c_has_bypass : integer;
|
||||
attribute c_has_bypass of U0 : label is 0;
|
||||
attribute c_has_c_in : integer;
|
||||
attribute c_has_c_in of U0 : label is 0;
|
||||
attribute c_has_c_out : integer;
|
||||
attribute c_has_c_out of U0 : label is 0;
|
||||
attribute c_latency : integer;
|
||||
attribute c_latency of U0 : label is 1;
|
||||
attribute c_out_width : integer;
|
||||
attribute c_out_width of U0 : label is 32;
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute is_du_within_envelope : string;
|
||||
attribute is_du_within_envelope of U0 : label is "true";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of CE : signal is "xilinx.com:signal:clockenable:1.0 ce_intf CE";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of CE : signal is "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_HIGH";
|
||||
attribute x_interface_info of CLK : signal is "xilinx.com:signal:clock:1.0 clk_intf CLK";
|
||||
attribute x_interface_parameter of CLK : signal is "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute x_interface_info of SCLR : signal is "xilinx.com:signal:reset:1.0 sclr_intf RST";
|
||||
attribute x_interface_parameter of SCLR : signal is "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
|
||||
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
|
||||
attribute x_interface_info of B : signal is "xilinx.com:signal:data:1.0 b_intf DATA";
|
||||
attribute x_interface_parameter of B : signal is "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
|
||||
attribute x_interface_info of S : signal is "xilinx.com:signal:data:1.0 s_intf DATA";
|
||||
attribute x_interface_parameter of S : signal is "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef";
|
||||
begin
|
||||
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_c_addsub_v12_0_15
|
||||
port map (
|
||||
A(15 downto 0) => A(15 downto 0),
|
||||
ADD => '1',
|
||||
B(31 downto 0) => B(31 downto 0),
|
||||
BYPASS => '0',
|
||||
CE => CE,
|
||||
CLK => CLK,
|
||||
C_IN => '0',
|
||||
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
|
||||
S(31 downto 0) => S(31 downto 0),
|
||||
SCLR => SCLR,
|
||||
SINIT => '0',
|
||||
SSET => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:53:32 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ c_add_s16_s32_stub.v
|
||||
// Design : c_add_s16_s32
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "c_addsub_v12_0_15,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(A, B, CLK, CE, SCLR, S)
|
||||
/* synthesis syn_black_box black_box_pad_pin="A[15:0],B[31:0],CE,SCLR,S[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input [15:0]A;
|
||||
input [31:0]B;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input CE;
|
||||
input SCLR;
|
||||
output [31:0]S;
|
||||
endmodule
|
||||
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:53:32 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ c_add_s16_s32_stub.vhdl
|
||||
-- Design : c_add_s16_s32
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
CLK : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
SCLR : in STD_LOGIC;
|
||||
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "A[15:0],B[31:0],CLK,CE,SCLR,S[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "c_addsub_v12_0_15,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
Reference in New Issue
Block a user