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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
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||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
// Date : Tue Sep 1 10:38:29 2026
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||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
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// Design : u_ila_0
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||||
// Purpose : Stub declaration of top-level module interface
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||||
// Device : xc7z020clg400-2
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||||
// --------------------------------------------------------------------------------
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||||
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "ila,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
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probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
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probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
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probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
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probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
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probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
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probe62, probe63, probe64)
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/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[15:0],probe3[7:0],probe4[0:0],probe5[7:0],probe6[15:0],probe7[31:0],probe8[7:0],probe9[1:0],probe10[15:0],probe11[15:0],probe12[1:0],probe13[8:0],probe14[15:0],probe15[7:0],probe16[15:0],probe17[8:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[7:0],probe22[7:0],probe23[15:0],probe24[15:0],probe25[7:0],probe26[12:0],probe27[31:0],probe28[3:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]" */
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/* synthesis syn_force_seq_prim="clk" */;
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input clk /* synthesis syn_isclock = 1 */;
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input [31:0]probe0;
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input [31:0]probe1;
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input [15:0]probe2;
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input [7:0]probe3;
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input [0:0]probe4;
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input [7:0]probe5;
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input [15:0]probe6;
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input [31:0]probe7;
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input [7:0]probe8;
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input [1:0]probe9;
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input [15:0]probe10;
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input [15:0]probe11;
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input [1:0]probe12;
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input [8:0]probe13;
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input [15:0]probe14;
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input [7:0]probe15;
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input [15:0]probe16;
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input [8:0]probe17;
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input [7:0]probe18;
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input [7:0]probe19;
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input [7:0]probe20;
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input [7:0]probe21;
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input [7:0]probe22;
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input [15:0]probe23;
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input [15:0]probe24;
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input [7:0]probe25;
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input [12:0]probe26;
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input [31:0]probe27;
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input [3:0]probe28;
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input [0:0]probe29;
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input [0:0]probe30;
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input [0:0]probe31;
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input [0:0]probe32;
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input [0:0]probe33;
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input [0:0]probe34;
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input [0:0]probe35;
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input [0:0]probe36;
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input [0:0]probe37;
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input [0:0]probe38;
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input [0:0]probe39;
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input [0:0]probe40;
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input [0:0]probe41;
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input [0:0]probe42;
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input [0:0]probe43;
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input [0:0]probe44;
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input [0:0]probe45;
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input [0:0]probe46;
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input [0:0]probe47;
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input [0:0]probe48;
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input [0:0]probe49;
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input [0:0]probe50;
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input [0:0]probe51;
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input [0:0]probe52;
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input [0:0]probe53;
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input [0:0]probe54;
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input [0:0]probe55;
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input [0:0]probe56;
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input [0:0]probe57;
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input [0:0]probe58;
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input [0:0]probe59;
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input [0:0]probe60;
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input [0:0]probe61;
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input [0:0]probe62;
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input [0:0]probe63;
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input [0:0]probe64;
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endmodule
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@@ -0,0 +1,96 @@
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||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Sep 1 10:38:29 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
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-- Design : u_ila_0
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-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7z020clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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clk : in STD_LOGIC;
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probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
probe13 : in STD_LOGIC_VECTOR ( 8 downto 0 );
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||||
probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe15 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
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||||
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe23 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe24 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe26 : in STD_LOGIC_VECTOR ( 12 downto 0 );
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||||
probe27 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
probe28 : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe64 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[15:0],probe3[7:0],probe4[0:0],probe5[7:0],probe6[15:0],probe7[31:0],probe8[7:0],probe9[1:0],probe10[15:0],probe11[15:0],probe12[1:0],probe13[8:0],probe14[15:0],probe15[7:0],probe16[15:0],probe17[8:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[7:0],probe22[7:0],probe23[15:0],probe24[15:0],probe25[7:0],probe26[12:0],probe27[31:0],probe28[3:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>194ab58acb1f218f</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_CHANN_EN_1</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_CHANN_EN_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">194ab58acb1f218f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">6d038ed3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
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+3227
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Load Diff
@@ -0,0 +1,48 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Nov 25 20:18:00 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_CHANN_EN_1_stub.v
|
||||
// Design : design_a9_1_CHANN_EN_1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o,
|
||||
gpio_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[2:0],gpio_io_o[2:0],gpio_io_t[2:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output ip2intc_irpt;
|
||||
input [2:0]gpio_io_i;
|
||||
output [2:0]gpio_io_o;
|
||||
output [2:0]gpio_io_t;
|
||||
endmodule
|
||||
@@ -0,0 +1,53 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Nov 25 20:18:00 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_CHANN_EN_1_stub.vhdl
|
||||
-- Design : design_a9_1_CHANN_EN_1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 2 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[2:0],gpio_io_o[2:0],gpio_io_t[2:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
Reference in New Issue
Block a user