sync chunk 8/12
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Aug 20 14:05:14 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
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||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
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probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
|
||||
probe62, probe63, probe64)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[31:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[1:0],probe7[15:0],probe8[7:0],probe9[31:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[15:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[8:0],probe22[15:0],probe23[7:0],probe24[7:0],probe25[7:0],probe26[31:0],probe27[3:0],probe28[12:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]" */
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/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]probe0;
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input [31:0]probe1;
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input [31:0]probe2;
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||||
input [15:0]probe3;
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input [7:0]probe4;
|
||||
input [7:0]probe5;
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||||
input [1:0]probe6;
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||||
input [15:0]probe7;
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||||
input [7:0]probe8;
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input [31:0]probe9;
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input [15:0]probe10;
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input [1:0]probe11;
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||||
input [7:0]probe12;
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||||
input [15:0]probe13;
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||||
input [15:0]probe14;
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input [15:0]probe15;
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input [8:0]probe16;
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input [15:0]probe17;
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input [7:0]probe18;
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input [7:0]probe19;
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input [7:0]probe20;
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||||
input [8:0]probe21;
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||||
input [15:0]probe22;
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||||
input [7:0]probe23;
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||||
input [7:0]probe24;
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||||
input [7:0]probe25;
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||||
input [31:0]probe26;
|
||||
input [3:0]probe27;
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||||
input [12:0]probe28;
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||||
input [0:0]probe29;
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||||
input [0:0]probe30;
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||||
input [0:0]probe31;
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||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
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||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
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||||
input [0:0]probe39;
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input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
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input [0:0]probe43;
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input [0:0]probe44;
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input [0:0]probe45;
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input [0:0]probe46;
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input [0:0]probe47;
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input [0:0]probe48;
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input [0:0]probe49;
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input [0:0]probe50;
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input [0:0]probe51;
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input [0:0]probe52;
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input [0:0]probe53;
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input [0:0]probe54;
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input [0:0]probe55;
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input [0:0]probe56;
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input [0:0]probe57;
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input [0:0]probe58;
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input [0:0]probe59;
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input [0:0]probe60;
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input [0:0]probe61;
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input [0:0]probe62;
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input [0:0]probe63;
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input [0:0]probe64;
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endmodule
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@@ -0,0 +1,96 @@
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Aug 20 14:05:14 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe21 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
probe27 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe64 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
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||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[31:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[1:0],probe7[15:0],probe8[7:0],probe9[31:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[15:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[8:0],probe22[15:0],probe23[7:0],probe24[7:0],probe25[7:0],probe26[31:0],probe27[3:0],probe28[12:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
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||||
begin
|
||||
end;
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||||
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@@ -0,0 +1,82 @@
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Nov 17 13:38:10 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[7:0],probe2[15:0],probe3[15:0],probe4[8:0],probe5[7:0],probe6[8:0],probe7[15:0],probe8[7:0],probe9[15:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[1:0],probe16[15:0],probe17[7:0],probe18[15:0],probe19[23:0],probe20[7:0],probe21[7:0],probe22[0:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [7:0]probe0;
|
||||
input [7:0]probe1;
|
||||
input [15:0]probe2;
|
||||
input [15:0]probe3;
|
||||
input [8:0]probe4;
|
||||
input [7:0]probe5;
|
||||
input [8:0]probe6;
|
||||
input [15:0]probe7;
|
||||
input [7:0]probe8;
|
||||
input [15:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [31:0]probe11;
|
||||
input [31:0]probe12;
|
||||
input [31:0]probe13;
|
||||
input [31:0]probe14;
|
||||
input [1:0]probe15;
|
||||
input [15:0]probe16;
|
||||
input [7:0]probe17;
|
||||
input [15:0]probe18;
|
||||
input [23:0]probe19;
|
||||
input [7:0]probe20;
|
||||
input [7:0]probe21;
|
||||
input [0:0]probe22;
|
||||
input [23:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Nov 17 13:38:10 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[7:0],probe2[15:0],probe3[15:0],probe4[8:0],probe5[7:0],probe6[8:0],probe7[15:0],probe8[7:0],probe9[15:0],probe10[7:0],probe11[31:0],probe12[31:0],probe13[31:0],probe14[31:0],probe15[1:0],probe16[15:0],probe17[7:0],probe18[15:0],probe19[23:0],probe20[7:0],probe21[7:0],probe22[0:0],probe23[23:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,83 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Jan 19 20:51:18 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[7:0],probe1[7:0],probe2[7:0],probe3[11:0],probe4[7:0],probe5[11:0],probe6[31:0],probe7[31:0],probe8[7:0],probe9[7:0],probe10[1:0],probe11[15:0],probe12[7:0],probe13[31:0],probe14[23:0],probe15[31:0],probe16[15:0],probe17[0:0],probe18[3:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [7:0]probe0;
|
||||
input [7:0]probe1;
|
||||
input [7:0]probe2;
|
||||
input [11:0]probe3;
|
||||
input [7:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [31:0]probe6;
|
||||
input [31:0]probe7;
|
||||
input [7:0]probe8;
|
||||
input [7:0]probe9;
|
||||
input [1:0]probe10;
|
||||
input [15:0]probe11;
|
||||
input [7:0]probe12;
|
||||
input [31:0]probe13;
|
||||
input [23:0]probe14;
|
||||
input [31:0]probe15;
|
||||
input [15:0]probe16;
|
||||
input [0:0]probe17;
|
||||
input [3:0]probe18;
|
||||
input [0:0]probe19;
|
||||
input [0:0]probe20;
|
||||
input [0:0]probe21;
|
||||
input [0:0]probe22;
|
||||
input [0:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
input [0:0]probe55;
|
||||
endmodule
|
||||
@@ -0,0 +1,87 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Jan 19 20:51:18 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[7:0],probe1[7:0],probe2[7:0],probe3[11:0],probe4[7:0],probe5[11:0],probe6[31:0],probe7[31:0],probe8[7:0],probe9[7:0],probe10[1:0],probe11[15:0],probe12[7:0],probe13[31:0],probe14[23:0],probe15[31:0],probe16[15:0],probe17[0:0],probe18[3:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
Binary file not shown.
File diff suppressed because one or more lines are too long
+252769
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,680 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>e74aea5a550047e3</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axi_smc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="smartconnect" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.ADDR_WIDTH">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
+20304
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jun 24 13:54:03 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_STIM_SPI_0_stub.v
|
||||
// Design : design_a9_1_STIM_SPI_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
|
||||
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
|
||||
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
|
||||
/* synthesis syn_force_seq_prim="ext_spi_clk" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input ext_spi_clk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [6:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [6:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input io0_i;
|
||||
output io0_o;
|
||||
output io0_t;
|
||||
input io1_i;
|
||||
output io1_o;
|
||||
output io1_t;
|
||||
input sck_i;
|
||||
output sck_o;
|
||||
output sck_t;
|
||||
input [0:0]ss_i;
|
||||
output [0:0]ss_o;
|
||||
output ss_t;
|
||||
output ip2intc_irpt;
|
||||
endmodule
|
||||
@@ -0,0 +1,63 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jun 24 13:54:03 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_STIM_SPI_0_stub.vhdl
|
||||
-- Design : design_a9_1_STIM_SPI_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
ext_spi_clk : in STD_LOGIC;
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
io0_i : in STD_LOGIC;
|
||||
io0_o : out STD_LOGIC;
|
||||
io0_t : out STD_LOGIC;
|
||||
io1_i : in STD_LOGIC;
|
||||
io1_o : out STD_LOGIC;
|
||||
io1_t : out STD_LOGIC;
|
||||
sck_i : in STD_LOGIC;
|
||||
sck_o : out STD_LOGIC;
|
||||
sck_t : out STD_LOGIC;
|
||||
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_t : out STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,69 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>ece357a95e34a6df</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_STIM_SPI_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_quad_spi" spirit:version="3.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_LITE.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LITE_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Async_Clk">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BYTE_LEVEL_INTERRUPT_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUAL_QUAD_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">axi_quad_spi_inst</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO1">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEMORY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEM_ADDR_BITS">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SUB_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_HIGHADDR">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_PERF_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_STIM_SPI_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_INCLUDED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_mode">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiples16">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.QSPI_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UC_FAMILY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">ece357a95e34a6df</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">ee7d7a68</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">103</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Wed Jun 24 05:54:28 UTC 2026
|
||||
Binary file not shown.
+17036
File diff suppressed because it is too large
Load Diff
+20304
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Nov 12 16:46:08 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_ZCHECK_SPI_0_stub.v
|
||||
// Design : design_a9_1_ZCHECK_SPI_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
|
||||
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
|
||||
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
|
||||
/* synthesis syn_force_seq_prim="ext_spi_clk" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input ext_spi_clk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [6:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [6:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input io0_i;
|
||||
output io0_o;
|
||||
output io0_t;
|
||||
input io1_i;
|
||||
output io1_o;
|
||||
output io1_t;
|
||||
input sck_i;
|
||||
output sck_o;
|
||||
output sck_t;
|
||||
input [0:0]ss_i;
|
||||
output [0:0]ss_o;
|
||||
output ss_t;
|
||||
output ip2intc_irpt;
|
||||
endmodule
|
||||
@@ -0,0 +1,63 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Nov 12 16:46:08 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_ZCHECK_SPI_0_stub.vhdl
|
||||
-- Design : design_a9_1_ZCHECK_SPI_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
ext_spi_clk : in STD_LOGIC;
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
io0_i : in STD_LOGIC;
|
||||
io0_o : out STD_LOGIC;
|
||||
io0_t : out STD_LOGIC;
|
||||
io1_i : in STD_LOGIC;
|
||||
io1_o : out STD_LOGIC;
|
||||
io1_t : out STD_LOGIC;
|
||||
sck_i : in STD_LOGIC;
|
||||
sck_o : out STD_LOGIC;
|
||||
sck_t : out STD_LOGIC;
|
||||
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ss_t : out STD_LOGIC;
|
||||
ip2intc_irpt : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,69 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>ed2a92631b34d8e8</spirit:name>
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||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_ZCHECK_SPI_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_quad_spi" spirit:version="3.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Async_Clk">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BYTE_LEVEL_INTERRUPT_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUAL_QUAD_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">axi_quad_spi_inst</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO1">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEMORY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEM_ADDR_BITS">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SUB_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_HIGHADDR">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_PERF_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_ZCHECK_SPI_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_INCLUDED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_mode">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiples16">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.QSPI_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UC_FAMILY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">ed2a92631b34d8e8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">ee7d7a68</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:5
|
||||
Timestamp: Tue Nov 25 12:16:20 UTC 2025
|
||||
Binary file not shown.
+980
@@ -0,0 +1,980 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:00:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_rst_ps7_0_50M_0_sim_netlist.v
|
||||
// Design : design_a9_1_rst_ps7_0_50M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_a9_1_rst_ps7_0_50M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_a9_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+1125
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:00:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_rst_ps7_0_50M_0_stub.v
|
||||
// Design : design_a9_1_rst_ps7_0_50M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
|
||||
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
|
||||
interconnect_aresetn, peripheral_aresetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="slowest_sync_clk" */;
|
||||
input slowest_sync_clk /* synthesis syn_isclock = 1 */;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:00:58 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_rst_ps7_0_50M_0_stub.vhdl
|
||||
-- Design : design_a9_1_rst_ps7_0_50M_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
slowest_sync_clk : in STD_LOGIC;
|
||||
ext_reset_in : in STD_LOGIC;
|
||||
aux_reset_in : in STD_LOGIC;
|
||||
mb_debug_sys_rst : in STD_LOGIC;
|
||||
dcm_locked : in STD_LOGIC;
|
||||
mb_reset : out STD_LOGIC;
|
||||
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,47 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>ed8878a20a900aa6</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_rst_ps7_0_50M_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_rst_ps7_0_50M_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">ed8878a20a900aa6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">a305ea60</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">89</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:3
|
||||
Timestamp: Thu Jul 02 09:34:13 UTC 2026
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,83 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 21 17:10:48 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[11:0],probe1[7:0],probe2[7:0],probe3[7:0],probe4[7:0],probe5[11:0],probe6[31:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[7:0],probe11[15:0],probe12[1:0],probe13[0:0],probe14[7:0],probe15[15:0],probe16[7:0],probe17[23:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [11:0]probe0;
|
||||
input [7:0]probe1;
|
||||
input [7:0]probe2;
|
||||
input [7:0]probe3;
|
||||
input [7:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [31:0]probe6;
|
||||
input [31:0]probe7;
|
||||
input [31:0]probe8;
|
||||
input [31:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [15:0]probe11;
|
||||
input [1:0]probe12;
|
||||
input [0:0]probe13;
|
||||
input [7:0]probe14;
|
||||
input [15:0]probe15;
|
||||
input [7:0]probe16;
|
||||
input [23:0]probe17;
|
||||
input [0:0]probe18;
|
||||
input [0:0]probe19;
|
||||
input [0:0]probe20;
|
||||
input [0:0]probe21;
|
||||
input [0:0]probe22;
|
||||
input [0:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
input [0:0]probe55;
|
||||
endmodule
|
||||
@@ -0,0 +1,87 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Wed Jan 21 17:10:48 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 23 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[7:0],probe2[7:0],probe3[7:0],probe4[7:0],probe5[11:0],probe6[31:0],probe7[31:0],probe8[31:0],probe9[31:0],probe10[7:0],probe11[15:0],probe12[1:0],probe13[0:0],probe14[7:0],probe15[15:0],probe16[7:0],probe17[23:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
+23148
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,71 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Nov 20 15:12:25 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.v
|
||||
// Design : design_a9_1_axi_dma_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_dma,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_lite_aclk, m_axi_mm2s_aclk, axi_resetn,
|
||||
s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr, s_axi_lite_wvalid,
|
||||
s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp, s_axi_lite_bvalid,
|
||||
s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready, s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata, s_axi_lite_rresp,
|
||||
m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid, m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast, m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata, m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast, mm2s_introut, axi_dma_tstvec)
|
||||
/* synthesis syn_black_box black_box_pad_pin="axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut,axi_dma_tstvec[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_lite_aclk" */
|
||||
/* synthesis syn_force_seq_prim="m_axi_mm2s_aclk" */;
|
||||
input s_axi_lite_aclk /* synthesis syn_isclock = 1 */;
|
||||
input m_axi_mm2s_aclk /* synthesis syn_isclock = 1 */;
|
||||
input axi_resetn;
|
||||
input s_axi_lite_awvalid;
|
||||
output s_axi_lite_awready;
|
||||
input [9:0]s_axi_lite_awaddr;
|
||||
input s_axi_lite_wvalid;
|
||||
output s_axi_lite_wready;
|
||||
input [31:0]s_axi_lite_wdata;
|
||||
output [1:0]s_axi_lite_bresp;
|
||||
output s_axi_lite_bvalid;
|
||||
input s_axi_lite_bready;
|
||||
input s_axi_lite_arvalid;
|
||||
output s_axi_lite_arready;
|
||||
input [9:0]s_axi_lite_araddr;
|
||||
output s_axi_lite_rvalid;
|
||||
input s_axi_lite_rready;
|
||||
output [31:0]s_axi_lite_rdata;
|
||||
output [1:0]s_axi_lite_rresp;
|
||||
output [31:0]m_axi_mm2s_araddr;
|
||||
output [7:0]m_axi_mm2s_arlen;
|
||||
output [2:0]m_axi_mm2s_arsize;
|
||||
output [1:0]m_axi_mm2s_arburst;
|
||||
output [2:0]m_axi_mm2s_arprot;
|
||||
output [3:0]m_axi_mm2s_arcache;
|
||||
output m_axi_mm2s_arvalid;
|
||||
input m_axi_mm2s_arready;
|
||||
input [31:0]m_axi_mm2s_rdata;
|
||||
input [1:0]m_axi_mm2s_rresp;
|
||||
input m_axi_mm2s_rlast;
|
||||
input m_axi_mm2s_rvalid;
|
||||
output m_axi_mm2s_rready;
|
||||
output mm2s_prmry_reset_out_n;
|
||||
output [31:0]m_axis_mm2s_tdata;
|
||||
output [3:0]m_axis_mm2s_tkeep;
|
||||
output m_axis_mm2s_tvalid;
|
||||
input m_axis_mm2s_tready;
|
||||
output m_axis_mm2s_tlast;
|
||||
output mm2s_introut;
|
||||
output [31:0]axi_dma_tstvec;
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Nov 20 15:12:25 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_dma_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_lite_aclk : in STD_LOGIC;
|
||||
m_axi_mm2s_aclk : in STD_LOGIC;
|
||||
axi_resetn : in STD_LOGIC;
|
||||
s_axi_lite_awvalid : in STD_LOGIC;
|
||||
s_axi_lite_awready : out STD_LOGIC;
|
||||
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_wvalid : in STD_LOGIC;
|
||||
s_axi_lite_wready : out STD_LOGIC;
|
||||
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_lite_bvalid : out STD_LOGIC;
|
||||
s_axi_lite_bready : in STD_LOGIC;
|
||||
s_axi_lite_arvalid : in STD_LOGIC;
|
||||
s_axi_lite_arready : out STD_LOGIC;
|
||||
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_rvalid : out STD_LOGIC;
|
||||
s_axi_lite_rready : in STD_LOGIC;
|
||||
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_mm2s_arvalid : out STD_LOGIC;
|
||||
m_axi_mm2s_arready : in STD_LOGIC;
|
||||
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_rlast : in STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : in STD_LOGIC;
|
||||
m_axi_mm2s_rready : out STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : out STD_LOGIC;
|
||||
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axis_mm2s_tvalid : out STD_LOGIC;
|
||||
m_axis_mm2s_tready : in STD_LOGIC;
|
||||
m_axis_mm2s_tlast : out STD_LOGIC;
|
||||
mm2s_introut : out STD_LOGIC;
|
||||
axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut,axi_dma_tstvec[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_dma,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,68 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>f2932a572cce8981</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:instanceName>design_a9_1_axi_dma_0_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dma" spirit:version="7.1"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_dma_0_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_addr_width">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_dlytmr_resolution">125</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm_dre">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_mm2s_data_width">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_micro_dma">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_mm2s_burst_size">128</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_mm2s_channels">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_s2mm_channels">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_prmry_is_aclk_async">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s2mm_burst_size">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_length_width">20</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_use_stsapp_length">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_single_interface">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">f2932a572cce8981</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">e8c2b284</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">29</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Wed Jun 24 05:51:52 UTC 2026
|
||||
Binary file not shown.
+1140
File diff suppressed because it is too large
Load Diff
+1119
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,54 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:00:58 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_bram_ctrl_0_0_stub.v
|
||||
// Design : design_a9_1_axi_bram_ctrl_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_bram_ctrl,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot,
|
||||
s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready,
|
||||
bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[12:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */
|
||||
/* synthesis syn_force_seq_prim="bram_clk_a" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [12:0]s_axi_awaddr;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [12:0]s_axi_araddr;
|
||||
input [2:0]s_axi_arprot;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output bram_rst_a;
|
||||
output bram_clk_a /* synthesis syn_isclock = 1 */;
|
||||
output bram_en_a;
|
||||
output [3:0]bram_we_a;
|
||||
output [12:0]bram_addr_a;
|
||||
output [31:0]bram_wrdata_a;
|
||||
input [31:0]bram_rddata_a;
|
||||
endmodule
|
||||
@@ -0,0 +1,58 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:00:58 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_bram_ctrl_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_bram_ctrl_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
bram_rst_a : out STD_LOGIC;
|
||||
bram_clk_a : out STD_LOGIC;
|
||||
bram_en_a : out STD_LOGIC;
|
||||
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[12:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,51 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>f4c93ad8ef68880e</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axi_bram_ctrl_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_bram_ctrl" spirit:version="4.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BMG_INSTANCE">EXTERNAL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_bram_ctrl_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC_ONOFF_RESET_VALUE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAULT_INJECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_DEPTH">2048</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_CMD_OPTIMIZATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_PORT_BRAM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">f4c93ad8ef68880e</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">425dc4e2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">89</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:27
|
||||
Timestamp: Thu Jul 02 09:34:13 UTC 2026
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
+23148
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,71 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:01:35 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.v
|
||||
// Design : design_a9_1_axi_dma_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_dma,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_lite_aclk, m_axi_mm2s_aclk, axi_resetn,
|
||||
s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr, s_axi_lite_wvalid,
|
||||
s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp, s_axi_lite_bvalid,
|
||||
s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready, s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata, s_axi_lite_rresp,
|
||||
m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid, m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast, m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata, m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast, mm2s_introut, axi_dma_tstvec)
|
||||
/* synthesis syn_black_box black_box_pad_pin="axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut,axi_dma_tstvec[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_lite_aclk" */
|
||||
/* synthesis syn_force_seq_prim="m_axi_mm2s_aclk" */;
|
||||
input s_axi_lite_aclk /* synthesis syn_isclock = 1 */;
|
||||
input m_axi_mm2s_aclk /* synthesis syn_isclock = 1 */;
|
||||
input axi_resetn;
|
||||
input s_axi_lite_awvalid;
|
||||
output s_axi_lite_awready;
|
||||
input [9:0]s_axi_lite_awaddr;
|
||||
input s_axi_lite_wvalid;
|
||||
output s_axi_lite_wready;
|
||||
input [31:0]s_axi_lite_wdata;
|
||||
output [1:0]s_axi_lite_bresp;
|
||||
output s_axi_lite_bvalid;
|
||||
input s_axi_lite_bready;
|
||||
input s_axi_lite_arvalid;
|
||||
output s_axi_lite_arready;
|
||||
input [9:0]s_axi_lite_araddr;
|
||||
output s_axi_lite_rvalid;
|
||||
input s_axi_lite_rready;
|
||||
output [31:0]s_axi_lite_rdata;
|
||||
output [1:0]s_axi_lite_rresp;
|
||||
output [31:0]m_axi_mm2s_araddr;
|
||||
output [7:0]m_axi_mm2s_arlen;
|
||||
output [2:0]m_axi_mm2s_arsize;
|
||||
output [1:0]m_axi_mm2s_arburst;
|
||||
output [2:0]m_axi_mm2s_arprot;
|
||||
output [3:0]m_axi_mm2s_arcache;
|
||||
output m_axi_mm2s_arvalid;
|
||||
input m_axi_mm2s_arready;
|
||||
input [31:0]m_axi_mm2s_rdata;
|
||||
input [1:0]m_axi_mm2s_rresp;
|
||||
input m_axi_mm2s_rlast;
|
||||
input m_axi_mm2s_rvalid;
|
||||
output m_axi_mm2s_rready;
|
||||
output mm2s_prmry_reset_out_n;
|
||||
output [31:0]m_axis_mm2s_tdata;
|
||||
output [3:0]m_axis_mm2s_tkeep;
|
||||
output m_axis_mm2s_tvalid;
|
||||
input m_axis_mm2s_tready;
|
||||
output m_axis_mm2s_tlast;
|
||||
output mm2s_introut;
|
||||
output [31:0]axi_dma_tstvec;
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:01:35 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axi_dma_0_0_stub.vhdl
|
||||
-- Design : design_a9_1_axi_dma_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_lite_aclk : in STD_LOGIC;
|
||||
m_axi_mm2s_aclk : in STD_LOGIC;
|
||||
axi_resetn : in STD_LOGIC;
|
||||
s_axi_lite_awvalid : in STD_LOGIC;
|
||||
s_axi_lite_awready : out STD_LOGIC;
|
||||
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_wvalid : in STD_LOGIC;
|
||||
s_axi_lite_wready : out STD_LOGIC;
|
||||
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_lite_bvalid : out STD_LOGIC;
|
||||
s_axi_lite_bready : in STD_LOGIC;
|
||||
s_axi_lite_arvalid : in STD_LOGIC;
|
||||
s_axi_lite_arready : out STD_LOGIC;
|
||||
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_rvalid : out STD_LOGIC;
|
||||
s_axi_lite_rready : in STD_LOGIC;
|
||||
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_mm2s_arvalid : out STD_LOGIC;
|
||||
m_axi_mm2s_arready : in STD_LOGIC;
|
||||
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_rlast : in STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : in STD_LOGIC;
|
||||
m_axi_mm2s_rready : out STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : out STD_LOGIC;
|
||||
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axis_mm2s_tvalid : out STD_LOGIC;
|
||||
m_axis_mm2s_tready : in STD_LOGIC;
|
||||
m_axis_mm2s_tlast : out STD_LOGIC;
|
||||
mm2s_introut : out STD_LOGIC;
|
||||
axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut,axi_dma_tstvec[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_dma,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,68 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>f6bdfb9e5296e01f</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axi_dma_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dma" spirit:version="7.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axi_dma_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_addr_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_dlytmr_resolution">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_enable_multi_channel">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s_dre">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s_sf">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm_dre">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_s2mm_sf">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_sg">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_increase_throughput">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_mm2s_data_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_micro_dma">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_mm2s_burst_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_mm2s_channels">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_num_s2mm_channels">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_prmry_is_aclk_async">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s2mm_burst_size">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_length_width">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_sg_use_stsapp_length">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_single_interface">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">f6bdfb9e5296e01f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">e8c2b284</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">126</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">29</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:3
|
||||
Timestamp: Thu Jul 02 09:34:13 UTC 2026
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -0,0 +1,99 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Sep 3 09:39:59 2026
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
|
||||
probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
|
||||
probe62, probe63, probe64, probe65, probe66, probe67, probe68, probe69, probe70)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[15:0],probe1[8:0],probe2[15:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[7:0],probe7[7:0],probe8[8:0],probe9[15:0],probe10[15:0],probe11[1:0],probe12[15:0],probe13[7:0],probe14[7:0],probe15[7:0],probe16[31:0],probe17[3:0],probe18[12:0],probe19[31:0],probe20[31:0],probe21[31:0],probe22[7:0],probe23[7:0],probe24[1:0],probe25[15:0],probe26[7:0],probe27[0:0],probe28[15:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0],probe67[0:0],probe68[0:0],probe69[0:0],probe70[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [15:0]probe0;
|
||||
input [8:0]probe1;
|
||||
input [15:0]probe2;
|
||||
input [15:0]probe3;
|
||||
input [7:0]probe4;
|
||||
input [7:0]probe5;
|
||||
input [7:0]probe6;
|
||||
input [7:0]probe7;
|
||||
input [8:0]probe8;
|
||||
input [15:0]probe9;
|
||||
input [15:0]probe10;
|
||||
input [1:0]probe11;
|
||||
input [15:0]probe12;
|
||||
input [7:0]probe13;
|
||||
input [7:0]probe14;
|
||||
input [7:0]probe15;
|
||||
input [31:0]probe16;
|
||||
input [3:0]probe17;
|
||||
input [12:0]probe18;
|
||||
input [31:0]probe19;
|
||||
input [31:0]probe20;
|
||||
input [31:0]probe21;
|
||||
input [7:0]probe22;
|
||||
input [7:0]probe23;
|
||||
input [1:0]probe24;
|
||||
input [15:0]probe25;
|
||||
input [7:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [15:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [0:0]probe39;
|
||||
input [0:0]probe40;
|
||||
input [0:0]probe41;
|
||||
input [0:0]probe42;
|
||||
input [0:0]probe43;
|
||||
input [0:0]probe44;
|
||||
input [0:0]probe45;
|
||||
input [0:0]probe46;
|
||||
input [0:0]probe47;
|
||||
input [0:0]probe48;
|
||||
input [0:0]probe49;
|
||||
input [0:0]probe50;
|
||||
input [0:0]probe51;
|
||||
input [0:0]probe52;
|
||||
input [0:0]probe53;
|
||||
input [0:0]probe54;
|
||||
input [0:0]probe55;
|
||||
input [0:0]probe56;
|
||||
input [0:0]probe57;
|
||||
input [0:0]probe58;
|
||||
input [0:0]probe59;
|
||||
input [0:0]probe60;
|
||||
input [0:0]probe61;
|
||||
input [0:0]probe62;
|
||||
input [0:0]probe63;
|
||||
input [0:0]probe64;
|
||||
input [0:0]probe65;
|
||||
input [0:0]probe66;
|
||||
input [0:0]probe67;
|
||||
input [0:0]probe68;
|
||||
input [0:0]probe69;
|
||||
input [0:0]probe70;
|
||||
endmodule
|
||||
@@ -0,0 +1,102 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Thu Sep 3 09:39:59 2026
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe64 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe65 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe66 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe67 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe68 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe69 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe70 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[15:0],probe1[8:0],probe2[15:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[7:0],probe7[7:0],probe8[8:0],probe9[15:0],probe10[15:0],probe11[1:0],probe12[15:0],probe13[7:0],probe14[7:0],probe15[7:0],probe16[31:0],probe17[3:0],probe18[12:0],probe19[31:0],probe20[31:0],probe21[31:0],probe22[7:0],probe23[7:0],probe24[1:0],probe25[15:0],probe26[7:0],probe27[0:0],probe28[15:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0],probe67[0:0],probe68[0:0],probe69[0:0],probe70[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
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@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Oct 28 21:01:04 2025
|
||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_1_0_stub.v
|
||||
// Design : design_a9_1_axis_data_fifo_1_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_data_fifo_v2_0_10_top,Vivado 2023.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axis_aresetn, s_axis_aclk, s_axis_tvalid,
|
||||
s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_tvalid, m_axis_tready,
|
||||
m_axis_tdata, m_axis_tkeep, m_axis_tlast, prog_full)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tkeep[0:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tkeep[0:0],m_axis_tlast,prog_full" */
|
||||
/* synthesis syn_force_seq_prim="s_axis_aclk" */;
|
||||
input s_axis_aresetn;
|
||||
input s_axis_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [7:0]s_axis_tdata;
|
||||
input [0:0]s_axis_tkeep;
|
||||
input s_axis_tlast;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [7:0]m_axis_tdata;
|
||||
output [0:0]m_axis_tkeep;
|
||||
output m_axis_tlast;
|
||||
output prog_full;
|
||||
endmodule
|
||||
@@ -0,0 +1,43 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Tue Oct 28 21:01:04 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_axis_data_fifo_1_0_stub.vhdl
|
||||
-- Design : design_a9_1_axis_data_fifo_1_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axis_tlast : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
m_axis_tlast : out STD_LOGIC;
|
||||
prog_full : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tkeep[0:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tkeep[0:0],m_axis_tlast,prog_full";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_data_fifo_v2_0_10_top,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>fa5045269e42d829</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_a9_1_axis_data_fifo_1_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_a9_1_axis_data_fifo_1_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">32768</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AFULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_FULL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_ACLK_ASYNC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_FULL_THRESH">32000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">fa5045269e42d829</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3850373 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">79870778</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">94</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,2 @@
|
||||
NumberHits:3
|
||||
Timestamp: Thu Jul 02 09:34:13 UTC 2026
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user