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c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/design_a9_1_STIM_SPI_0.dcp
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c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/design_a9_1_STIM_SPI_0_sim_netlist.v
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c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/design_a9_1_STIM_SPI_0_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/design_a9_1_STIM_SPI_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jun 24 13:54:03 2026
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_STIM_SPI_0_stub.v
// Design : design_a9_1_STIM_SPI_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_quad_spi,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */
/* synthesis syn_force_seq_prim="ext_spi_clk" */
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
input ext_spi_clk /* synthesis syn_isclock = 1 */;
input s_axi_aclk /* synthesis syn_isclock = 1 */;
input s_axi_aresetn;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [6:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
output ip2intc_irpt;
endmodule
c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/design_a9_1_STIM_SPI_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Jun 24 13:54:03 2026
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_STIM_SPI_0_stub.vhdl
-- Design : design_a9_1_STIM_SPI_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2023.1";
begin
end;
c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/ece357a95e34a6df.xci
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>xilinx.com</spirit:vendor>
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c64_pro.cache/ip/2023.1/e/c/ece357a95e34a6df/stats.txt
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Timestamp: Wed Jun 24 05:54:28 UTC 2026