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chunk-sync
2026-09-11 16:18:02 +08:00
parent 2fd31447be
commit 18a979ac62
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c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/dec4a0d810193243.xci
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c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/u_ila_0.dcp
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c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/u_ila_0_sim_netlist.v
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c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/u_ila_0_sim_netlist.vhdl
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c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/u_ila_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Thu Aug 20 14:05:14 2026
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
// Design : u_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2023.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50,
probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61,
probe62, probe63, probe64)
/* synthesis syn_black_box black_box_pad_pin="probe0[31:0],probe1[31:0],probe2[31:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[1:0],probe7[15:0],probe8[7:0],probe9[31:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[15:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[8:0],probe22[15:0],probe23[7:0],probe24[7:0],probe25[7:0],probe26[31:0],probe27[3:0],probe28[12:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]" */
/* synthesis syn_force_seq_prim="clk" */;
input clk /* synthesis syn_isclock = 1 */;
input [31:0]probe0;
input [31:0]probe1;
input [31:0]probe2;
input [15:0]probe3;
input [7:0]probe4;
input [7:0]probe5;
input [1:0]probe6;
input [15:0]probe7;
input [7:0]probe8;
input [31:0]probe9;
input [15:0]probe10;
input [1:0]probe11;
input [7:0]probe12;
input [15:0]probe13;
input [15:0]probe14;
input [15:0]probe15;
input [8:0]probe16;
input [15:0]probe17;
input [7:0]probe18;
input [7:0]probe19;
input [7:0]probe20;
input [8:0]probe21;
input [15:0]probe22;
input [7:0]probe23;
input [7:0]probe24;
input [7:0]probe25;
input [31:0]probe26;
input [3:0]probe27;
input [12:0]probe28;
input [0:0]probe29;
input [0:0]probe30;
input [0:0]probe31;
input [0:0]probe32;
input [0:0]probe33;
input [0:0]probe34;
input [0:0]probe35;
input [0:0]probe36;
input [0:0]probe37;
input [0:0]probe38;
input [0:0]probe39;
input [0:0]probe40;
input [0:0]probe41;
input [0:0]probe42;
input [0:0]probe43;
input [0:0]probe44;
input [0:0]probe45;
input [0:0]probe46;
input [0:0]probe47;
input [0:0]probe48;
input [0:0]probe49;
input [0:0]probe50;
input [0:0]probe51;
input [0:0]probe52;
input [0:0]probe53;
input [0:0]probe54;
input [0:0]probe55;
input [0:0]probe56;
input [0:0]probe57;
input [0:0]probe58;
input [0:0]probe59;
input [0:0]probe60;
input [0:0]probe61;
input [0:0]probe62;
input [0:0]probe63;
input [0:0]probe64;
endmodule
c64_pro.cache/ip/2023.1/d/e/dec4a0d810193243/u_ila_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Thu Aug 20 14:05:14 2026
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
-- Design : u_ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
probe7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe14 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe15 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe17 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe24 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe27 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe28 : in STD_LOGIC_VECTOR ( 12 downto 0 );
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe64 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0],probe2[31:0],probe3[15:0],probe4[7:0],probe5[7:0],probe6[1:0],probe7[15:0],probe8[7:0],probe9[31:0],probe10[15:0],probe11[1:0],probe12[7:0],probe13[15:0],probe14[15:0],probe15[15:0],probe16[8:0],probe17[15:0],probe18[7:0],probe19[7:0],probe20[7:0],probe21[8:0],probe22[15:0],probe23[7:0],probe24[7:0],probe25[7:0],probe26[31:0],probe27[3:0],probe28[12:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.1";
begin
end;