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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
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||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
// Date : Tue Oct 28 21:01:00 2025
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||||
// Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_CHANN_EN_1_stub.v
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// Design : design_a9_1_CHANN_EN_1
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-2
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||||
// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_gpio,Vivado 2023.1" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
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s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
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s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
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s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
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/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[2:0],gpio_io_o[2:0],gpio_io_t[2:0]" */
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/* synthesis syn_force_seq_prim="s_axi_aclk" */;
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input s_axi_aclk /* synthesis syn_isclock = 1 */;
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input s_axi_aresetn;
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input [8:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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||||
input s_axi_wvalid;
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output s_axi_wready;
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||||
output [1:0]s_axi_bresp;
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||||
output s_axi_bvalid;
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||||
input s_axi_bready;
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||||
input [8:0]s_axi_araddr;
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||||
input s_axi_arvalid;
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||||
output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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input [2:0]gpio_io_i;
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output [2:0]gpio_io_o;
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output [2:0]gpio_io_t;
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endmodule
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||||
@@ -0,0 +1,52 @@
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||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
-- Date : Tue Oct 28 21:01:00 2025
|
||||
-- Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_a9_1_CHANN_EN_1_stub.vhdl
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-- Design : design_a9_1_CHANN_EN_1
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||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7z020clg400-2
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||||
-- --------------------------------------------------------------------------------
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||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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s_axi_aclk : in STD_LOGIC;
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s_axi_aresetn : in STD_LOGIC;
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||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
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||||
s_axi_awvalid : in STD_LOGIC;
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||||
s_axi_awready : out STD_LOGIC;
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||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_wvalid : in STD_LOGIC;
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||||
s_axi_wready : out STD_LOGIC;
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||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
s_axi_bvalid : out STD_LOGIC;
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||||
s_axi_bready : in STD_LOGIC;
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||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
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||||
s_axi_arvalid : in STD_LOGIC;
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||||
s_axi_arready : out STD_LOGIC;
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||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
s_axi_rvalid : out STD_LOGIC;
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||||
s_axi_rready : in STD_LOGIC;
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||||
gpio_io_i : in STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
gpio_io_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
gpio_io_t : out STD_LOGIC_VECTOR ( 2 downto 0 )
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||||
);
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||||
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||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
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||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[2:0],gpio_io_o[2:0],gpio_io_t[2:0]";
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||||
attribute x_core_info : string;
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||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2023.1";
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||||
begin
|
||||
end;
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||||
@@ -0,0 +1,740 @@
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|
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</spirit:configurableElementValues>
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</spirit:componentInstance>
|
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</spirit:componentInstances>
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</spirit:design>
|
||||
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Reference in New Issue
Block a user