Date : 2024-03-26 15:29:43
Directory : d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl
Total : 55 files,  8710 codes, 1239 comments, 1945 blanks, all 11894 lines

Languages
+----------+------------+------------+------------+------------+------------+
| language | files      | code       | comment    | blank      | total      |
+----------+------------+------------+------------+------------+------------+
| Verilog  |         54 |      8,403 |      1,104 |      1,896 |     11,403 |
| VHDL     |          1 |        307 |        135 |         49 |        491 |
+----------+------------+------------+------------+------------+------------+

Directories
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+
| path                                                                                       | files      | code       | comment    | blank      | total      |
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+
| .                                                                                          |         55 |      8,710 |      1,239 |      1,945 |     11,894 |
| . (Files)                                                                                  |          5 |      1,281 |        185 |        293 |      1,759 |
| accel                                                                                      |          2 |        314 |         23 |         67 |        404 |
| eeg                                                                                        |         10 |      1,567 |        223 |        325 |      2,115 |
| emg                                                                                        |          2 |        125 |         31 |         42 |        198 |
| rhs2116                                                                                    |         21 |      3,833 |        581 |        878 |      5,292 |
| switch                                                                                     |          4 |        413 |         69 |         89 |        571 |
| trigger                                                                                    |          3 |        203 |         31 |         55 |        289 |
| upload                                                                                     |          3 |        491 |         41 |        101 |        633 |
| utils                                                                                      |          5 |        483 |         55 |         95 |        633 |
+--------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+

Files
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+
| filename                                                                                   | language | code       | comment    | blank      | total      |
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\accel_top.v                 | Verilog  |        117 |         13 |         36 |        166 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\lis2dw12.v                  | Verilog  |        197 |         10 |         31 |        238 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\c64pro_top.v                      | Verilog  |        364 |         44 |         78 |        486 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_arrange.v             | Verilog  |        195 |         16 |         31 |        242 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_if.v                  | Verilog  |        149 |         18 |         27 |        194 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_mod.v                 | Verilog  |        113 |         13 |         29 |        155 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi - backup.v        | Verilog  |        186 |         12 |         29 |        227 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi.v                 | Verilog  |        218 |         10 |         35 |        263 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi_tb.v              | Verilog  |         79 |         16 |         21 |        116 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_config.v                  | Verilog  |        118 |         16 |         32 |        166 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top.v                     | Verilog  |        204 |         21 |         52 |        277 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top_tb.v                  | Verilog  |        158 |         88 |         40 |        286 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_upload.v                  | Verilog  |        147 |         13 |         29 |        189 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_config.v                  | Verilog  |         81 |         14 |         25 |        120 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_top.v                     | Verilog  |         44 |         17 |         17 |         78 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl.v                        | Verilog  |         58 |         10 |         12 |         80 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl_tb.v                     | Verilog  |         34 |         19 |         17 |         70 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top.v                          | Verilog  |        320 |         35 |         70 |        425 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top_tb.v                       | Verilog  |        505 |         77 |        116 |        698 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect.v         | Verilog  |        180 |         14 |         30 |        224 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect_tb.v      | Verilog  |        119 |         20 |         33 |        172 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.v        | Verilog  |         74 |         16 |         21 |        111 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.vhd      | VHDL     |        307 |        135 |         49 |        491 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_mod.v             | Verilog  |         84 |          7 |         19 |        110 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top.v             | Verilog  |        337 |         27 |         86 |        450 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top_tb.v          | Verilog  |        367 |         26 |         83 |        476 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen.v                | Verilog  |        154 |         22 |         31 |        207 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen_tb.v             | Verilog  |        129 |         18 |         42 |        189 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_event_collect.v      | Verilog  |         74 |         10 |         14 |         98 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_monitor.v            | Verilog  |        105 |         13 |         14 |        132 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange.v           | Verilog  |        174 |         18 |         31 |        223 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange_tb.v        | Verilog  |        268 |         19 |         62 |        349 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute.v        | Verilog  |        120 |         13 |         26 |        159 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute_tb.v     | Verilog  |        114 |         16 |         24 |        154 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer.v             | Verilog  |         60 |         10 |         15 |         85 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer_tb.v          | Verilog  |         55 |         15 |         19 |         89 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config.v         | Verilog  |        351 |         82 |         74 |        507 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config_tb.v      | Verilog  |        321 |         36 |        101 |        458 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if.v             | Verilog  |        268 |         25 |         46 |        339 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if_tb.v          | Verilog  |        172 |         39 |         58 |        269 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if.v               | Verilog  |        136 |         13 |         25 |        174 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if_tb.v            | Verilog  |         56 |         15 |         17 |         88 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch.v           | Verilog  |        169 |         25 |         30 |        224 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch_tb.v        | Verilog  |         52 |         16 |         17 |         85 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_detection.v       | Verilog  |         21 |          1 |          7 |         29 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top.v             | Verilog  |        137 |         15 |         32 |        184 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top_tb.v          | Verilog  |         45 |         15 |         16 |         76 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_config.v            | Verilog  |         96 |         14 |         29 |        139 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_sort.v              | Verilog  |        141 |         12 |         27 |        180 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_top.v               | Verilog  |        254 |         15 |         45 |        314 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\breath_gen.v                | Verilog  |        123 |         13 |         25 |        161 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\debouncing.v                | Verilog  |         93 |         10 |         15 |        118 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\pwm_gen.v                   | Verilog  |         40 |          4 |          9 |         53 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master.v    | Verilog  |        148 |         12 |         25 |        185 |
| d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master_tb.v | Verilog  |         79 |         16 |         21 |        116 |
| Total                                                                                      |          |      8,710 |      1,239 |      1,945 |     11,894 |
+--------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+